2-2
Internal Architecture
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
Figure 2-1. Internal Architecture, with Pipeline Stage
1
5
2
3
4
Fetch
Decode
Load
Store
Execute
8 Ports
64
Result
Retire
Fastpath
Hardware ROPs
M Code
Microcode ROPs
R.S.
Reservation Station
Port
41 bits
Address
Data
32
8 Ports
4 Ports
5 Ports
2 Po
rt
s
Load
Store
Prefetch & Predecode
Branch Prediction
Instruction
Cache
Linear Tags
Byte
Queue
Fast
Path
M
Code
Fast
Path
M
Code
Fast
Path
M
Code
Fast
Path
M
Code
R.S.
R.S.
ALU
R.S.
ALU
R.S.
Branch
R.S.
FPU
Load
Store
Load
Store
Reorder Buffer
(ROB)
Register File
(x86 GPRs, FPRs)
Memory Management Unit
(TLBs and Physical Tags)
Bus Interface Unit
Data
Cache
Linear Tags
Store
Buffer
4 Ports
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...