Control Register 4 (CR4) Extensions
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18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
In addition to these performance problems caused by virtual-
ization of the IF flag in Virtual-8086 mode, software interrupts
(those caused by INTn instructions that vector through inter-
rupt gates) cannot be masked by the IF flag or virtual copies of
the IF flag, these flags only affect hardware interrupts. Soft-
ware interrupts in Virtual-8086 mode are normally directed to
the Real mode interrupt vector table (IVT), but it may be
desirable to redirect interrupts for certain vectors to the Pro-
tected mode interrupt descriptor table (IDT).
The processor’s Virtual-8086 mode extensions support both of
these cases—hardware (external) interrupts and software
interrupts—with mechanisms that preserve high performance
without compromising protection. Virtualization of hardware
interrupts is supported via the Virtual Interrupt Flag (VIF)
and Virtual Interrupt Pending (VIP) flag in the EFLAGS regis-
ter. Redirection of software interrupts is supported with the
Interrupt Redirection Bitmap (IRB) in the TSS of each Virtual-
8086 program.
Hardware Interrupts
and the VIF and VIP
Extensions
When VME extensions are enabled, the IF-modifying instruc-
tions that are normally trapped by the operating system are
allowed to execute, but they write and read the VIF bit rather
than the IF bit in EFLAGS. This leaves maskable interrupts
enabled for detection by the operating system. It also indicates
to the operating system whether the Virtual-8086 program is
able to or expecting to receive interrupts.
When an external interrupt occurs, the processor switches
from the Virtual-8086 program to the operating system, in the
same manner as on a 386 or 486 processor. If the operating sys-
tem determines that the interrupt is for the Virtual-8086 pro-
gram, it checks the state of the VIF bit in the program’s
EFLAGS image on the stack. If VIF has been set by the proces-
sor (during an attempt by the program to set the IF bit), the
operating system permits access to the appropriate Virtual-
8086 handler via the interrupt vector table (IVT). If VIF has
been cleared, the operating system holds the interrupt pend-
ing. The operating system can do this by saving appropriate
information (such as the interrupt vector), setting the pro-
gram's VIP flag in the EFLAGS image on the stack, and return-
ing to the interrupted program. When the program
subsequently attempts to set IF, the set VIP flag causes the
processor to inhibit the instruction and generate a general-
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...