Signal Descriptions
5-33
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
5.2.8
BE7–BE0 (Byte Enables)
Output
Summary
The eight bits of BE7–BE0, when cleared to 0, validate the
eight bytes driven on D63–D0. In this way, BE7–BE0 expands
on the function of address bits A2–A0, which do not exist on
the A31–A3 address bus. BE7–BE0 also help differentiate the
special bus cycles.
Driven and Floated
The processor drives BE7–BE0 from the clock in which ADS is
asserted until the last expected BRDY of the bus cycle. The
processor floats BE7–BE0 one clock after system logic asserts
BOFF and in the same clock that the processor asserts HLDA.
BE7–BE0 is driven with the address and cycle definition out-
puts (D/C, M/IO and W/R) during memory cycles (including
cache writethroughs and writebacks), I/O cycles, locked cycles,
special bus cycles, and interrupt acknowledge operations in
the normal operating modes (Real, Protected, and Virtual-
8086) and in SMM, or while PRDY is asserted. While AHOLD is
asserted, BE7–BE0 is driven only to complete a bus cycle that
had been initiated before AHOLD was asserted, or for inquire
cycle writebacks. During the Shutdown, Halt, and Stop Grant
states, BE7–BE0 is driven only for inquire cycle writebacks.
BE7–BE0 is not driven during the Stop Clock state, or while
BOFF, HLDA, RESET, or INIT is asserted.
Details
Table 5-5 shows the relationship between BE7–BE0, D63–D0,
DP7–DP0, and the effective relationship with A2–A0, the non-
existent low address bits. The BE7–BE0 signals expand on the
function of A2–A0; BE7–BE0 allow the processor to address
any or all eight bytes indicated by A31–A3, whereas A2–A0, if
they existed, would only address one of eight bytes.
During single-transfer memory cycles and all I/O cycles, the
processor drives BE7–BE0 to identify all of the bytes desired
for the transfer. System logic must return valid data in those
byte lanes of D63–D0.
During burst reads (CACHE and KEN both asserted with the
first BRDY of a memory read), the processor drives BE7–BE0
with ADS to identify the bytes of the desired instruction or
operand. The processor drives BE7–BE0 with the desired bytes
at that time because it does not yet know whether the read will
be a single-transfer or a burst—this depends on how system
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...