5-112
Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
Unlike INIT, RESET reinitializes the processor’s entire state.
In particular, RESET differs by reinitializing the contents of
the caches, floating-point registers, control registers, and
model-specific registers, as well as all other states that are
reinitialized by INIT.
A20M should not be asserted during RESET. The operating
system alone is responsible for controlling the state of A20M
by writing to an external register provided for this purpose.
(See the description of A20M on page 5-18.)
Because the processor boots in Real mode, the memory address
decoder must alias the physical address FFFF_FFF0h to the
physical address 000F_FFF0h, which lies within the 1-Mbyte
Table 5-16. Outputs at RESET
Output
RESET State
ADS
1
A31–A3
Floating
APCHK
1
BE7–BE0
FFh
BREQ
1
BRDY
1
BRDYC
1
CACHE
1
D/C
0
D63–D0
Floating
DP7–DP0
00h
FERR
1
HIT
1
HITM
1
HLDA
0
LOCK
1
M/IO
0
PCD
0
PCHK
1
PRDY
0
PWT
0
W/R
0
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...