Cache and TLB Testing
7-13
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
Figure 7-6. Test Formats: Instruction-Cache Instructions
EDX: Array Pointer
0
31 30 29 28 27
0 0
Array ID
(E4h)
Way
0 0 0 0 0 0 0 0
Set
0
EAX: Test Data
(E4h) Instruction Bytes
7
20 19
9
8
11
12
Opcode
Bytes
0
0 0 0 0 0 0
Valid Bits
31
26 25
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...