5-16
Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
The processor recognizes BOFF, HOLD, and AHOLD while any
interrupt signal is asserted, and these signals will intervene
with their normal timing in the handling of any interrupt or
exception. The interrupt or exception continues from where it
left off after the intervening signal is negated. For example, if
BOFF is asserted while a FLUSH operation is writing modified
Table 5-3. Summary of Interrupts and Exceptions
Priority
Description
Type
Sampling
5
Vector
1
Acknowledgment
Point of Interruptibility
6
1
INTn instruc-
tions and all
other software
exceptions
exceptions
internal
0-255
none
Entry to service routine.
2
BUSCHK
interrupt
level-sensitive
18
2
none
Entry to service routine.
2
3
R/S
interrupt
level-sensitive
none
PRDY
Negation of PRDY.
4
FLUSH
interrupt
edge-triggered
4
none
FLUSH-Acknowl-
edge special
bus cycle
BRDY of FLUSH Acknowl-
edge bus cycle.
5
SMI
interrupt
edge-triggered
4
SMM
3
SMIACT
Entry to SMM service
routine.
7
6
INIT
interrupt
edge-triggered
4
BIOS
none
Completion of
initialization.
7
NMI
interrupt
edge-triggered
4
2
none
NMI interrupts: IRET from
service routine. All others:
Entry to service routine.
8
INTR
interrupt
level-sensitive
0-255
Interrupt acknowl-
edge special
bus cycle
Entry to service routine.
9
STPCLK
interrupt
level-sensitive
none
Stop-Grant
special bus cycle
Negation of STPCLK.
Notes:
1. For interrupts with vectors, the processor saves its state prior to accessing service routine and changing program flow. Interrupts
without vectors do not change program flow; instead, they simply pause program flow for the duration of the interrupt function
and then return to where they left off.
2. If the machine check enable (MCE) bit in CR4 is set to 1.
3. The entry point for the SMI interrupt handler is at offset 8000h from the SMM Base Address.
4. Only the edge-triggered interrupts are latched when asserted. All interrupts are recognized at the next instruction retirement
boundary.
5. If a bus cycle is in progress, EWBE must be asserted before the interrupt is recognized.
6. For external interrupts (most exceptions, by contrast, are recognized when they occur). External interrupts are recognized at
instruction boundaries. MOV or POP instructions that load SS delay interruptibility until after the next instruction, thus allowing both
SS and the corresponding SP to load.
7. After assertion of SMI, subsequent assertions of SMI are masked so as to prevent recursive entry into SMM. Other exceptions or
interrupts (except INIT and NMI), however, will intervene in the SMM service routine.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...