5-18
Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
5.2.1
A20M (Address Bit 20 Mask)
Input
Summary
Assertion of A20M causes the processor to clear bit 20 of the
A31–A3 address bus to 0 prior to accessing the cache or mem-
ory in Real mode. The clearing of address bit 20 bit maps
addresses above 1 Mbyte to addresses below 1 Mbyte.
Sampled
The processor samples A20M in every clock during Real mode.
System logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously driven setup
and hold times).
A20M is sampled only in Real mode during memory cycles
(including cache writethroughs and writebacks) and locked
cycles; or while AHOLD, BOFF, HLDA, RESET, INIT, or PRDY
is asserted. A20M is not sampled when the processor is operat-
ing in Protected mode, Virtual-8086 mode or SMM; during I/O
cycles, inquire cycles, special bus cycles, or interrupt acknowl-
edge operations; or while the processor is in the Shutdown,
Halt, Stop Grant, or Stop Clock states.
Details
The action of clearing A20 so that addresses above 1MB wrap-
around to addresses below 1 Mbyte simulates the behavior of
the 8086 processor, allowing the processor to run software
designed for DOS. A20M should only be asserted when the pro-
cessor runs in Real mode.
A20M should not be asserted during the first code fetch follow-
ing the RESET or INIT cycles because the masking of bit 20
leads to a fetch from an incorrect address. The BIOS and the
operating system alone are responsible for controlling the
state of A20M. After RESET or INIT, they do this by writing to
an external I/O port. (I/O ports 60 and 64h, or port 92h, or regis-
ter-shadowed versions of those ports are commonly used to
control the state of A20M.) The instruction pipeline is serial-
ized by virtue of writing to the I/O port, thus allowing time for
the A20M signal to assert before the next memory or cache
access. Advanced operating systems that do not run under
DOS, such as Windows NT™ and OS/2 operating systems, do
not use Real mode and never assert A20M.
Programs running in Virtual-8086 mode run as tasks under Pro-
tected mode. The effect of A20M for these Virtual-8086-mode
tasks is normally emulated by the operating system using the
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...