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AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
5.2.40 PCHK (Parity Status) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-101
5.2.41 PEN (Parity Enable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-102
5.2.42 PRDY (Probe Ready) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-103
5.2.43 PWT (Page Writethrough) . . . . . . . . . . . . . . . . . . . . . . . . . . 5-105
5.2.44 R/S (Run or Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-107
5.2.45 RESET (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-109
5.2.46 SCYC (Split Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-114
5.2.47 SMI (System Management Interrupt) . . . . . . . . . . . . . . . . . 5-116
5.2.48 SMIACT (System Management Interrupt Active) . . . . . . . 5-121
5.2.49 STPCLK (Stop Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-122
5.2.50 TCK (Test Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-127
5.2.51 TDI (Test Data Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-128
5.2.52 TDO (Test Data Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-129
5.2.53 TMS (Test Mode Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-130
5.2.54 TRST (Test Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-131
5.2.55 W/R (Write or Read) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-132
5.2.56 WB/WT (Writeback or Writethrough) . . . . . . . . . . . . . . . . . 5-133
5.3 Bus Cycle Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136
5.3.1
Cycle Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-136
5.3.2
Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-137
5.3.3
Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-137
5.3.4
Bus Speed and Typical DRAM Timing . . . . . . . . . . . . . . . . 5-139
5.3.5
Bus-Cycle Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-139
5.4 Bus Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140
5.4.1
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-140
5.4.2
Single-Transfer Reads and Writes . . . . . . . . . . . . . . . . . . . . 5-141
Single-Transfer Memory Read and Write . . . . . . . . . . . . . . 5-141
Single-Transfer Memory Write Delayed by EWBE Signal 5-144
I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-146
Single-Transfer Misaligned Memory and I/O Transfers . . 5-147
5.4.3
Burst Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-149
Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-149
Burst Writeback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-153
5.4.4
Bus Arbitration and Inquire Cycles . . . . . . . . . . . . . . . . . . . 5-156
AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . . . . 5-157
AHOLD-Initiated Inquire Hit to Shared or
Exclusive Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-159
AHOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . 5-160
Bus Backoff (BOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-162
BOFF-Initiated Inquire Hit to Modified Line . . . . . . . . . . . 5-164
HOLD-Initiated Inquire Hit to Shared or Exclusive Line . 5-166
HOLD-Initiated Inquire Hit to Modified Line . . . . . . . . . . 5-168
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...