7-4
Test and Debug
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
Table 7-1. Hardware Configuration Register (HWCR) Fields
Bit
Mnemonic
Description
Function
31–8
—
—
reserved
7
DDC
Disable Data Cache
Disables data cache.
0 = enabled, 1 = disabled.
6
DIC
Disable Instruction Cache
Disables instruction cache.
0 = enabled, 1 = disabled.
5
DBP
Disable Branch Prediction
Disables branch prediction.
0 = enabled, 1 = disabled.
4
—
—
reserved
3–1
DC
Debug Control
Debug control bits:
000
Off (disable HWCR debug control).
001
Enable branch-tracing messages. See Section
7.6 on page 7-17.
010
reserved
011
reserved
100
reserved
101
reserved
110
reserved
111
reserved
0
DSPC
Disable Stopping
Processor Clocks
Disables stopping of internal processor clocks in the
Halt and Stop Grant states.
0 = enabled, 1 = disabled.
Notes:
Documentation on the Hardware Debug Tool (HDT) is available from AMD under a nondisclosure agreement.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...