A-14
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
A.6
Exceptions
A.6.1
Limit Faults on an Invalid Instruction
When executing an instruction that crosses a limit boundary
and the instruction is interpreted as invalid, the AMD-K5 pro-
cessor prioritizes the invalid opcode fault. The Pentium and
486 processors prioritize the limit violation fault.
A.6.2
Task Switch
On a task switch, the AMD-K5 processor sets the busy bit of the
incoming task after storing the outgoing TSS according to 486
and Pentium processor documentation. The Pentium processor
sets the busy bit before trying to store the outgoing TSS. If a
fault occurs while trying to store the TSS, the Pentium proces-
sor clears the busy bit. The end result of the instruction is the
same on both processors.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...