3-16
Software Environment and Extensions
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
Table 3-5A through Table 3-5E shows the effects, in various
x86-processor modes, of instructions that read or write the IF
and VIF flag. The column headings in this table include the fol-
lowing values:
■
PE—Protection Enable bit in CR0 (bit 0)
■
VM—Virtual-8086 Mode bit in EFLAGS (bit 17)
■
VME—Virtual Mode Extensions bit in CR4 (bit 0)
■
PVI—Protected-mode Virtual Interrupts bit in CR4 (bit 1)
■
IOPL—I/O Privilege Level bits in EFLAGS (bits 13–12)
■
Handler CPL—Code Privilege Level of the interrupt
handler
■
GP(0)—General-protection exception, with error code = 0
■
IF—Interrupt Flag bit in EFLAGS (bit 9)
■
VIF—Virtual Interrupt Flag bit in EFLAGS (bit 19)
Table 3-5A.
Instructions that Modify the IF or VIF Flags—Real Mode
TYPE
PE
VM
VME
PVI
IOPL
GP(0)
IF
VIF
CLI
0
0
0
0
—
No
IF
←
0
—
STI
0
0
0
0
—
No
IF
←
1
—
PUSHF
0
0
0
0
—
No
Pushed
—
POPF
0
0
0
0
—
No
Popped
—
IRET
0
0
0
0
—
No
Popped
—
Notes:
— Not applicable.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...