Clock Control
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18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
During SMM, the Pentium processor does not respond to NMI
until the beginning of its response to the first INTR or software
interrupt (INTn) to occur after entering SMM. NMIs can thus
be enabled by using a dummy interrupt. When an INTR or soft-
ware interrupt is recognized, the processor first responds to a
pending NMI interrupt before executing the first instruction of
the INTR handler. By contrast, the AMD-K5 processor recog-
nizes a pending NMI interrupt after returning (via the IRET
instruction) from a prior interrupt.
The same dummy interrupt used on the Pentium processor to
enable NMI recognition during SMM works on the AMD-K5
processor. The only difference is that the AMD-K5 processor
responds to the NMI after the IRET of the dummy interrupt
whereas the Pentium processor responds at the beginning of
the dummy interrupt. All other exceptions and interrupts
within SMM are fully compatible with those supported by the
Pentium processor in SMM.
The IF flag in EFLAGS is cleared automatically when the pro-
cessor enters SMM, thus disabling maskable interrupts. The
HLT instruction should not be executed in SMM without first
setting the IF bit.
Table 5-2 on page 5-8 and Table 5-3 on page 5-16 summarize the
behavior of all interrupts in SMM.
6.3.9
SMM Compatibility with Pentium Processor
The differences in SMM functions between the AMD-K5 and
Pentium processors are described in Section A.5 on page A-12.
6.4
Clock Control
The processor’s consumption of power can be controlled by
reducing the frequency of the processor and/or bus clocks
when there is no computational or user activity. System logic
initiates this control by asserting STPCLK, which causes the
processor to complete any in-progress bus cycle and enter the
Stop Grant state (processor’s internal clock stopped), from
which system logic can subsequently transition the processor
to its Stop Clock state (CLK stopped). These clock control func-
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...