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Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
name, some PC systems allow the interrupt to be masked with
a write to an I/O port (such as port 70h).
Upon recognizing an NMI interrupt at the next instruction
retirement boundary, the processor performs the following
actions, in the order shown:
1. Flush Pipeline—The processor invalidates all instructions
remaining in the pipeline.
2. Service Interrupt—The processor saves its state and
accesses vector 2 in the interrupt vector table (IVT) or
interrupt descriptor table (IDT), depending on whether the
processor is running in Real mode or Protected mode. The
vector identifies a gate descriptor in the table. The IDT, for
example, can contain interrupt, trap, or task gates, all of
which point indirectly to the entry point of an interrupt ser-
vice routine.
The processor recognizes BOFF, HOLD, and AHOLD while
NMI is asserted and these signals will intervene in the NMI ser-
vice routine. The processor latches the assertion of any edge-
triggered interrupt (FLUSH, SMI, INIT, NMI) while BUSCHK
is asserted and recognizes latched interrupts in priority order
when BUSCHK is negated. If NMI is asserted during the Stop
Grant state, the signal is held pending until after the processor
exits the Stop Grant state, at which point it is acted upon.
During SMM, the Pentium processor does not respond to NMI
until the beginning of its response to the first INTR or software
interrupt (INTn) to occur after entering SMM. NMIs can thus
be enabled by using a dummy interrupt. When an INTR or soft-
ware interrupt is recognized, the processor first responds to a
pending NMI interrupt before executing the first instruction of
the INTR handler. By contrast, the AMD-K5 processor recog-
nizes a pending NMI interrupt after returning (via the IRET
instruction) from a prior interrupt.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...