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Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
Shutdown Cycle
Figure 5-21 shows a shutdown and the special cycle that fol-
lows. The processor enters shutdown when an interrupt or
exception occurs during the handling of a double fault (vector
8), which amounts to a triple fault. When the processor encoun-
ters such a triple fault, it stops its activity on the bus and gen-
erates the special bus cycle for shutdown (BE7–BE0 = FEh).
System logic must respond with BRDY.
System logic must assert NMI, INIT, RESET, or SMI to get the
processor out of the Shutdown state.
Figure 5-21. Shutdown Cycle
CLK
A31–A3
ADS
BE7–BE0
BRDY
CACHE
D/C
D63–D0
INTR
KEN
LOCK
M/IO
W/R
CLK
Shutdown
Occurs
Shutdown
Special
Cycle
…
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...