6-40
System Design
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
6.6
Power-Up Requirements
During power-up, CLK should be toggling and RESET should
be asserted as V
CC
is ramping toward normal operating volt-
age. Figure 6-7 shows this timing. After V
CC
and CLK reach
specification, RESET must be asserted for a minimum of 1 ms
to allow the phase-lock loop to synchronize.
Figure 6-7. V
cc
and CLK
RESET must be asserted
for at least 1 ms after V
CC
and CLK are stable.
CLK
RESET
≥
1 ms
PWRGOOD
V
CC
at Operating Voltage
V
CC
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...