Memory
6-7
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
Figure 6-2. Default SMM Memory Map
System logic controls the cacheability of SMM memory with
KEN in the same way that it controls the cacheability of mem-
ory space. If SMM memory is to be non-cacheable, KEN must
be held negated from when SMI is asserted until SMIACT is
negated. If SMM memory is to be cacheable, KEN must be
asserted for cacheable read cycles.
SMM
State-Save
Area
SMM Base Address (CS)
Service Routine Entry Point
Fill Down
SMM
Service Routine
32-Kbyte
Minimum
RAM
0003_8000
0003_FE00
0003_FFFF
0003_0000
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...