viii
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
6.3.8
Exceptions and Interrupts in SMM . . . . . . . . . . . . . . . . . . . . 6-32
6.3.9
SMM Compatibility with Pentium Processor . . . . . . . . . . . . 6-33
6.4 Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-33
6.4.1
State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
6.4.2
Halt State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-34
6.4.3
Stop Grant State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
6.4.4
Stop Grant Inquire State . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-37
6.4.5
Stop Clock State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
6.4.6
Clock Control Compatibility with Pentium Processor . . . . 6-38
6.5 Power and Ground Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-38
6.6 Power-Up Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-40
6.7 Noise Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-41
6.8 Thermal Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-42
6.9 Design Support and Peripheral Products . . . . . . . . . . . . . . . . 6-43
7 Test and Debug
7-1
7.1 Hardware Configuration Register (HWCR) . . . . . . . . . . . . . . . 7-3
7.2 Built-In Self Test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.1
Normal BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5
7.2.2
Test Access Port (TAP) BIST . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6
7.3 Output-Float Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4 Cache and TLB Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7
7.4.1
Array Access Register (AAR) . . . . . . . . . . . . . . . . . . . . . . . . . 7-8
7.4.2
Array Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9
7.4.3
Array Test Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10
7.5 Debug Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.5.1
Standard Debug Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.5.2
I/O Breakpoint Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
7.5.3
Debug Compatibility with Pentium Processor . . . . . . . . . . . 7-17
7.6 Branch Tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
7.7 Functional-Redundancy Checking . . . . . . . . . . . . . . . . . . . . . . 7-18
7.8 Boundary-Scan Test Access Port (TAP) . . . . . . . . . . . . . . . . . . 7-19
7.8.1
Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . 7-21
7.8.2
Public Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-22
7.9 Hardware Debug Tool (HDT) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-23
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...