5-116
Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
5.2.47
SMI (System Management Interrupt)
Input
Summary
The assertion of SMI causes the processor to enter System
Management Mode (SMM). In this mode, which can be trans-
parent to standard system and application software, an SMM
interrupt service routine accesses a memory space separate
from main memory. SMM is most commonly used for power
management, although it is not limited to these functions.
Sampled and
Acknowledged
The processor samples SMI every clock and recognizes it at the
next instruction boundary. SMI is a falling-edge-triggered
interrupt with an internal pullup resistor. It is latched when
sampled. When recognized, SMI is acknowledged with SMI-
ACT after the later of (a) the last expected BRDY of any in-
progress bus cycle, or (b) the assertion of EWBE with or follow-
ing the last expected BRDY. SMI must be negated for at least
four clocks before being asserted. It must be asserted at least
three clocks before BRDY if it is to be recognized on the
instruction boundary associated with that BRDY.
SMI is sampled during memory cycles (including cache
writethroughs and writebacks), cache accesses, I/O cycles,
locked cycles, special bus cycles, and interrupt acknowledge
operations in the normal operating modes (Real, Protected,
and Virtual-8086) and in SMM; in the Shutdown, Halt, or Stop
Grant states; or while AHOLD, BOFF, or HLDA is asserted.
SMI is not sampled in the Stop Clock state, or while RESET,
INIT, or PRDY is asserted.
SMI is the fourth-highest-priority external interrupt. For
details on its relationship to other interrupts and exceptions,
see Section 5.1.3 on page 5-13 and Table 5-3 on page 5-16.
System logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously-driven setup
and hold times).
Details
SMI is typically driven by a power management block of sys-
tem logic that monitors activity on processor outputs, such as
the address and cycle definition signals in conjunction with a
timer. An SMM interrupt service routine in firmware controls
events during SMM. The most common applications involve
power management via clock and/or I/O device control. For
example, the external power management logic may notice
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...