5-122
Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
5.2.49
STPCLK (Stop Clock)
Input
Summary
The assertion of STPCLK causes the processor to complete any
in-progress bus cycle and enter the Stop Grant state (proces-
sor’s internal clock stopped), from which it can subsequently
transition to the Stop Clock state (bus clock stopped). These
low-power clock states can be entered from the normal operat-
ing modes, system management mode (SMM), or the Halt state.
Sampled and
Acknowledged
The processor samples STPCLK every clock and recognizes it
at the next instruction boundary. STPCLK is a level-sensitive
interrupt with an internal pullup resistor. The signal must be
held asserted until recognized. When STPCLK is recognized
and EWBE is asserted, the processor acknowledges it by driv-
ing a Stop Grant special bus cycle, waits for BRDY, then stops
its internal clock and floats D63–D0 and DP7–DP0.
STPCLK is sampled during memory cycles (including cache
writethroughs and writebacks), cache accesses, I/O cycles,
locked cycles, special bus cycles, and interrupt acknowledge
operations in the normal operating modes (Real, Protected,
and Virtual-8086) and in SMM; or in the Shutdown, Halt, or
Stop Grant states. STPCLK is not sampled in the Stop Clock
state, or while RESET, INIT, or PRDY is asserted. STPCLK is
not meaningful if it is asserted while AHOLD, BOFF, or HLDA
is asserted, because the processor cannot drive the Stop Grant
special bus cycle.
STPCLK is the lowest-priority external interrupt. For details
on its relationship to other interrupts and exceptions, see Sec-
tion 5.1.3 on page 5-13 and Table 5-3 on page 5-16.
System logic can drive the signal either synchronously or asyn-
chronously (see the data sheet for synchronously driven setup
and hold times).
Details
In typical PC systems that implement power control, the STP-
CLK, CLK, and SMI signals are driven by external power man-
agement logic. This logic monitors activity on the address and
cycle definition signals. In a typical case, the power manage-
ment logic may notice that, after having initiated SMM to
power down one or more I/O devices, another several minutes
have elapsed without activity. Power management logic can
again assert SMI, the SMM service routine would obtain the
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...