5-106
Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
the accessed line is cached in, transitions to, or remains in the
shared state after the access. If PWT is Low and WB/WT
is
High, the accessed line is cached in, transitions to, or remains
in the exclusive state after a read miss or the first write hit. A
subsequent write to an exclusive line changes it to modified.
The state of the PWT output is based on the state of several
bits written by the operating system. In Protected mode, the
PWT output applies to the entire current page rather than to
the specific bus cycle that the WB/WT output applies to, and it
is the operating system’s (rather than the processor hard-
ware’s) determination of writeback or writethrough state.
The bits that determine the PWT output are stored in a proces-
sor control register or the TLB. Those bits include the paging
enable (PG) bit in CR0 and the page writethrough (PWT) bit in
one of three locations. The selection of bits depends on the pro-
cessor’s operating mode and the type of access, as follows:
■
In Real mode, and in Protected and Virtual-8086 modes
while paging is disabled (PG bit in CR0 cleared to 0):
PWT output = Low (writeback)
■
In Protected and Virtual-8086 modes while paging is
enabled (PG bit in CR0 set to 1):
For accesses to I/O space, page directory entries, and other
non-paged accesses:
PWT output = PWT bit in CR3
For accesses to 4-Kbyte page table entries or 4-Mbyte
pages:
PWT output = PWT bit in page directory entry
For accesses to a 4-Kbyte pages:
PWT output = PWT bit in page table entry
The method of selecting the PWT bit is similar to that for the
PCD bit as described on page 5-99. The cache disable (CD) and
not-writethrough (NW) bits in CR0 are cleared to 0 for normal,
cacheable operation.
In the Hardware Debug Tool (HDT) mode, PWT is only mean-
ingful for cache write misses (PWT = 0 and WB/WT = 1 transi-
tion a shared line to an exclusive line). The signal is not
meaningful during cache read misses in HDT mode, because
the caches are never filled during HDT mode.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...