2-22
Internal Architecture
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
Internal Snooping
The processor automatically snoops its instruction cache dur-
ing read or write misses to its data cache, and it snoops its data
cache during read misses to its instruction cache. It does this to
detect the presence of self-modifying code. Table 2-4 summa-
rizes the actions taken during this internal snooping.
Table 2-4. Snoop Action
Origin of
Snoop
Type of Access
Snooping Action
Instructions
Data
Instruction
Cache
Prefetch
Cache
Data
Cache
Store
Buffer
Writeback
Buffers
External
Inquire Cycle
yes
1
yes
yes
1
no
yes
1
Internal
Instruction
Cache
Read
Miss
—
—
yes
2
yes
2
yes
2
Read
Hit
—
—
no
no
no
Data
Cache
Read
Miss
yes
3
yes
3
—
—
—
Read
Hit
no
no
—
—
—
Write
Miss
yes
4
yes
4
—
—
—
Write
Hit
no
no
—
—
—
Notes:
1. The processor’s response to a snoop hit depends on the state of the INV input signal and the state of the cache line as follows:
For instructions if INV is negated, the line remains invalid or shared, but if INV is asserted, the line is invalidated. For data if INV is
negated, valid lines remain in or transition to the shared state, a modified data cache line is written back before the line is marked
shared (with HITM asserted), invalid lines remain invalid.
For data if INV is asserted, the line is marked invalid. Modified lines are written back before invalidation.
2. If the snoop hits a line in the data cache, store buffer or writeback buffer, the line is written back (if modified) and invalidated.
Then the instruction-cache read is performed again. If the line is modified, a copy of the writeback data is passed directly to the
instruction cache, thus avoiding a line-fill bus cycle after the writeback bus cycle.
3. If the snoop hits a line in the instruction cache, prefetch cache, or line-fill buffer, the line stays valid and the data-cache read is
performed again, but as a single, non-cacheable read.
4. If the snoop hits a line in the instruction cache, prefetch cache, or line-fill buffer, the line is invalidated and the data-cache write is
performed.
— Not applicable.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...