5-142
Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
BRDY, the processor latches the physical address and cycle
definition of the failed bus cycle in its 64-bit machine-check
address register (MCAR) and its 64-bit machine-check type
register (MCTR). For details on such parity errors, see the
descriptions of PCHK and PEN on pages 5-101 and 5-102.
While Figure 5-2 shows BRDY returned in the next clock after
ADS, most DRAM-based systems add wait states (idle clocks)
between ADS and BRDY.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...