Bus Cycle Overview
5-137
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AMD-K5 Processor Technical Reference Manual
the signals shown in Table 5-23 on page 5-180. In addition to
the processor-driven bus cycles shown in Table 5-19, system
logic can drive inquire cycles to the processor. These bus
cycles are described later, in Section 5.4.4 on page 5-156.
The processor samples BRDY during all bus cycles that it
drives. The number of BRDYs expected by the processor
depends on the type of bus cycle, as follows:
■
One BRDY for an aligned single-transfer read or write
cycle, a special bus cycle, and each of two bus cycles in an
interrupt acknowledge operation. One additional BRDY for
each misaligned cycle.
■
Four BRDYs for burst cycles (one BRDY for each of the four
transfers). Burst cycles are always aligned.
The last expected BRDY represents the completion of a proces-
sor-initiated bus cycle. The processor guarantees at least one
idle clock between consecutive bus cycles, whether unlocked
or locked. This means that consecutive locked operations,
which consist of consecutive bus cycles, also have at least one
idle clock between them.
5.3.2
Addressing
The address for a bus cycle is driven on A31–A3 and BE7–BE0.
A31–A3 carry the upper 29 bits of the address, identifying an
aligned 8-byte (quadword) region in memory. BE7–BE0 iden-
tify the accessed bytes in that quadword, in effect indicating
the three least-significant bits of the address and the size (in
bytes) of the desired transfer. For burst and inquire cycles,
A31–A5 are sufficient to identify the memory location of the
cache line. For burst reads, which are four-transfer cache-line
fills, system logic should watch A4–A3 and return the
addressed quadword first, before returning the remainder of
the cache line.
More details on burst-cycle addressing are given in Section
5.4.3 on page 5-149.
5.3.3
Alignment
For purposes of bus cycles, the term aligned means:
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...