Signal Descriptions
5-133
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
5.2.56
WB/WT (Writeback or Writethrough)
Input
Summary
WB/WT, together with PWT, specifies the data-cache MESI
state of cacheable read misses and write hits.
Sampled
The processor samples WB/WT in the same clock as the first
BRDY of a bus cycle or NA, whichever comes first.
WB/WT is sampled during memory reads and writes, including
writebacks, in the normal operating modes (Real, Protected,
and Virtual-8086) and SMM, and when PRDY is asserted. WB/
WT is not sampled during I/O cycles, locked cycles, special bus
cycles, or interrupt acknowledge operations; or during the
Shutdown, Halt, Stop Grant, or Stop Clock states; or while
BOFF, HLDA, RESET, or INIT is asserted. While AHOLD is
asserted, WB/WT is sampled only to complete a bus cycle
begun before the assertion of AHOLD.
Details
Lines in the shared MESI state are said to be in the
writethrough state. Those in the exclusive or modified MESI
state are said to be in the writeback state. When a write access
either misses the data cache or hits a shared line in the data
cache, the processor drives a 1-to-8-byte write cycle (called a
writethrough) on the bus. When an inquire cycle, internal
snoop, FLUSH operation, or WBINVD instruction hits a modi-
fied line in the data cache, the processor drives a 32-byte burst
write cycle (called a writeback) on the bus. Table 2-2 on page 2-
19 shows the relationships between cache accesses,
writethroughs, and writebacks.
WB/WT and PWT determine the MESI state of a cache line
after a read miss (and resulting cache-line fill) or a write hit.
During read misses, these two signals are interpreted along
with the states of the CACHE output and the KEN input. Dur-
ing write hits, WB/WT and PWT alone determine the resulting
MESI state of a cache line. Tables 5-17 and 5-18 shows the rela-
tionship between WB/WT and PWT for reads (Table 5-17) and
writes (Table 5-18). If WB/WT is Low or PWT is High during a
read miss or write hit, the accessed line is cached in, transi-
tions to, or remains in the shared state after the read or write.
If PWT is Low and WB/WT is High, the accessed line is cached
in, transitions to, or remains in the exclusive state after a read
miss or the first write hit to that line. If the line transitions to
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...