5-72
Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
5.2.26
HITM (Inquire Cycle Hit To Modified Line)
Output
Summary
The processor asserts HITM to indicate that an inquire cycle
hit a modified line in the processor’s data cache. If this occurs,
the processor writes the line back to memory during or after
the bus-hold tenure, depending on which signal is holding the
processor off the bus. HIT is always asserted whenever HITM
is asserted.
Driven
The processor drives HITM every clock. The signal changes
state two clocks after the assertion of EADS. If the inquire
cycle misses the cache or hits an exclusive or shared line in the
cache, the processor holds HITM negated and another inquire
cycle can begin in that clock (two clocks after EADS). If the
inquire cycle hits a modified line in the data cache, the proces-
sor asserts HITM and holds it asserted until one clock after the
last BRDY of the writeback, then negates it.
HITM is driven at all times, except while the processor is in the
Stop Clock state, or while RESET or INIT is asserted.
Details
The processor asserts HITM when an inquire cycle address
matches the address of a modified line in the processor’s data
cache. The processor then attempts to drive a four-transfer
burst writeback of the modified line. If INV was asserted at the
time EADS was asserted for the inquire cycle, a hit leaves the
written-back line in the invalid state. If INV was negated at the
time EADS was asserted, a hit leaves the written-back line in
the shared state. For a comparison of the states that HITM,
HIT, and INV can assume, see Table 5-11 on page 5-71.
System logic can use HITM to inhibit access to the bus by other
masters (via BOFF or HOLD) until the writeback associated
with the hit has completed. The time at which the writeback
occurs depends on which input signal was used to hold the pro-
cessor off the bus for the inquire cycle:
■
If AHOLD was used, the processor drives the writeback as
early as two clocks after asserting HITM, whether or not
AHOLD is still asserted at that time.
■
If BOFF or HOLD was used, the processor delays the write-
back until after BOFF or HLDA is negated. In the case of
BOFF, the writeback is driven before any aborted bus cycle
is restarted.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...