iv
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
3 Software Environment and Extensions
3-1
3.1 Control Register 4 (CR4) Extensions . . . . . . . . . . . . . . . . . . . . . 3-2
3.1.1
Machine-Check Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.1.2
4-Mbyte Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.1.3
Global Pages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.1.4
Virtual-8086 Mode Extensions (VME) . . . . . . . . . . . . . . . . . 3-12
Interrupt Redirection in Virtual-8086 Mode
Without VME Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Hardware Interrupts and the VIF and VIP Extensions . . . . 3-13
Software Interrupts and the Interrupt Redirection
Bitmap (IRB) Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
3.1.5
Protected Virtual Interrupt (PVI) Extensions . . . . . . . . . . . 3-24
3.2 Model-Specific Registers (MSRs) . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.2.1
Machine-Check Address Register (MCAR) . . . . . . . . . . . . . 3-25
3.2.2
Machine-Check Type Register (MCTR) . . . . . . . . . . . . . . . . 3-26
3.2.3
Time Stamp Counter (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.2.4
Array Access Register (AAR) . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.2.5
Hardware Configuration Register (HWCR) . . . . . . . . . . . . . 3-28
3.3 New Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.3.1
CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-29
3.3.2
CMPXCHG8B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.3.3
MOV to and from CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
3.3.4
RDTSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.3.5
RDMSR and WRMSR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3.3.6
RSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3.3.7
Illegal Instruction (Reserved Opcode) . . . . . . . . . . . . . . . . . 3-36
4 Performance
4-1
4.1 Code Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.1
General Superscalar Techniques . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1.2
Techniques Specific to the AMD-K5 Processor . . . . . . . . . . . 4-3
4.2 Dispatch and Execution Timing . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.1
Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4.2.2
Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8
4.2.3
Integer Dot Product Example . . . . . . . . . . . . . . . . . . . . . . . . 4-17
4.2.4
Floating-Point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...