xi
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
List of Figures
Figure 2-1.
Internal Architecture, with Pipeline Stage . . . . . . . . . . . 2-2
Figure 2-2.
Pipeline Stage Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Figure 3-1.
Control Register 4 (CR4) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Figure 3-2.
4-Kbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . 3-5
Figure 3-3.
4-Mbyte Paging Mechanism . . . . . . . . . . . . . . . . . . . . . . . . 3-6
Figure 3-4.
Page-Directory Entry (PDE). . . . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3-5.
Page-Table Entry (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Figure 3-6.
EFLAGS Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Figure 3-7.
Task State Segment (TSS) . . . . . . . . . . . . . . . . . . . . . . . . 3-22
Figure 3-8.
Machine-Check Address Register (MCAR) . . . . . . . . . . 3-25
Figure 3-9.
Machine-Check Type Register (MCTR) . . . . . . . . . . . . . 3-26
Figure 5-1.
Signal Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Figure 5-2.
Single-Transfer Memory Read and Write. . . . . . . . . . . 5-143
Figure 5-3.
Single-Transfer Memory Write Delayed
by EWBE Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-145
Figure 5-4.
I/O Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-146
Figure 5-5.
Single-Transfer Misaligned Memory and
I/O Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-148
Figure 5-6.
Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-151
Figure 5-7.
Burst Read (NA Sampled) . . . . . . . . . . . . . . . . . . . . . . . 5-152
Figure 5-8.
Burst Writeback Due To Cache-Line Replacement . . . 5-155
Figure 5-9.
AHOLD-Initiated Inquire Miss . . . . . . . . . . . . . . . . . . . 5-158
Figure 5-10.
AHOLD-Initiated Inquire Hit to Shared
or Exclusive Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-159
Figure 5-11.
AHOLD-Initiated Inquire Hit to Modified Line. . . . . . 5-161
Figure 5-12.
Basic BOFF Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 5-163
Figure 5-13.
BOFF-Initiated Inquire Hit to Modified Line. . . . . . . . 5-165
Figure 5-14.
HOLD-Initiated Inquire Hit to Shared
or Exclusive Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-167
Figure 5-15.
HOLD-Initiated Inquire Hit to Modified Line . . . . . . . 5-168
Figure 5-16.
Basic Locked Operation . . . . . . . . . . . . . . . . . . . . . . . . . 5-170
Figure 5-17.
TLB Miss (4-Kbyte Page) . . . . . . . . . . . . . . . . . . . . . . . . 5-172
Figure 5-18.
Locked Operation with BOFF Intervention . . . . . . . . . 5-174
Figure 5-19A.
Interrupt Acknowledge Operation Part 1. . . . . . . . . . . 5-177
Figure 5-19B.
Interrupt Acknowledge Operation Part 2. . . . . . . . . . . 5-178
Figure 5-19C.
Interrupt Acknowledge Operation Part 3. . . . . . . . . . . 5-179
Figure 5-20.
Basic Special Bus Cycle (Halt Cycle) . . . . . . . . . . . . . . 5-181
Figure 5-21.
Shutdown Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-182
Figure 5-22.
FLUSH-Acknowledge Cycle . . . . . . . . . . . . . . . . . . . . . . 5-183
Figure 5-23.
Cache-Invalidation Cycle (INVD Instruction) . . . . . . . 5-184
Figure 5-24A.
Cache-Writeback and Invalidation Cycle
(WBINVD Instruction) Part 1 . . . . . . . . . . . . . . . . . . . . 5-185
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...