Copyright © January 2014 Lattice Semiconductor Corporation.
LatticeMico GPIO
The LatticeMico GPIO is a general-purpose input/output core that provides a
memory-mapped interface between a WISHBONE slave port and general-
purpose I/O ports. The I/O ports can connect to either on-chip or off-chip logic.
Version
This document describes the 3.5 version of the LatticeMico GPIO.
Features
The LatticeMico GPIO includes the following features:
WISHBONE B.3 interface
WISHBONE data base size configurable to 8 or 32 bits wide
Four transfer port types: tristate, input, output, independent input/output
Interrupt request (IRQ) generation on level-sensitive or edge-sensitive
input
Hardware interrupt mask register
Figure 1 shows the deployment of the LatticeMico GPIO within the FPGA and
its input and output ports.
For additional details about the WISHBONE bus, refer to the
LatticeMico8
Processor Reference Manual
or the
LatticeMico32 Processor Reference
Manual
.
