Hardware Configuration Register (HWCR)
7-3
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
7.1
Hardware Configuration Register (HWCR)
The Hardware Configuration Register (HWCR) is a model-spe-
cific register (MSR) that contains configuration bits that
enable cache, branch tracing, debug, and clock control func-
tions. The WRMSR and RDMSR instructions access the HWCR
when the ECX register contains the value 83h, as described in
Section 3.3.5 on page 3-33. Figure 7-1 and Table 7-1 show the
format and fields of the HWCR.
Figure 7-1. Hardware Configuration Register (HWCR)
Disable Data Cache
DDC
7
Disable Instruction Cache
DIC
6
Disable Branch Prediction
DBP
5
Debug Control
DC
3–1
000
Off
001
Enable branch trace usages
Disable Stopping Processor Clocks
DSPC
0
8
7
6
5
4
3
2
1
0
31
D
I
C
D
D
C
D
B
P
D
C
D
S
P
C
Reserved
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...