Control Register 4 (CR4) Extensions
3-21
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
Software Interrupts
and the Interrupt
Redirection Bitmap
(IRB) Extension
In Virtual-8086 mode, software interrupts (INTn exceptions
that vector through interrupt gates) are trapped by the operat-
ing system for emulation, because they would otherwise clear
the real IF. When VME extensions are enabled, these INTn
instructions are allowed to execute normally, vectoring
directly to a Virtual-8086 service routine via the Virtual-8086
interrupt vector table (IVT) at address 0 of the task address
space. However, it may still be desirable for security or perfor-
mance reasons to intercept INTn instructions on a vector-spe-
cific basis to allow servicing by Protected-mode routines
accessed through the interrupt descriptor table (IDT). This is
accomplished by an Interrupt Redirection Bitmap (IRB) in the
TSS, which is created by the operating system in a manner sim-
ilar to the IO Permission Bitmap (IOPB) in the TSS.
Figure 3-7 shows the format of the TSS, with the Interrupt
Redirection Bitmap near the top. The IRB contains 256 bits,
one for each possible software-interrupt vector. The most-sig-
nificant bit of the IRB is located immediately below the base of
the IOPB. This bit controls interrupt vector 255. The least-sig-
nificant bit of the IRB controls interrupt vector 0.
The bits in the IRB work as follows:
■
Set—If set to 1, the INTn instruction behaves as if the VME
extensions are not enabled. The interrupt vectors to a Pro-
tected-mode routine if IOPL = 3, or it causes a general-pro-
tection exception with error code zero if IOPL<3.
■
Cleared—If cleared to 0, the INTn instruction vectors
directly to the corresponding Virtual-8086 service routine
via the Virtual-8086 program’s IVT.
Only software interrupts can be redirected via the IRB to a
Real mode IVT—hardware interrupts cannot. Hardware inter-
rupts are asynchronous events and do not belong to any cur-
rent virtual task. The processor thus has no way of deciding
which IVT (for which Virtual-8086 program) to direct a hard-
ware interrupt to. Because of this, hardware interrupts always
require operating system intervention. The VIF and VIP bits
described on page 3-13 are provided to assist the operating sys-
tem in this intervention.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...