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Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
BREQ asserted continuously. For a list of signals recognized
while AHOLD is asserted, see Table 5-2 on page 5-8.
The processor may again drive its own cycles with ADS as early
as one clock after system logic negates AHOLD. Before negat-
ing AHOLD, however, system logic may need to arbitrate
among potential contenders for the address bus so as to avoid
deadlock contention for the bus.
Ground-bounce spikes can be avoided by following two rules
with respect to AHOLD:
■
Do not negate AHOLD in the same clock that BRDY is
asserted during a write cycle.
■
Do not negate AHOLD in the same clock that ADS is
asserted during a writeback.
These restrictions must be observed because the processor’s 32
address drivers turn on almost immediately after AHOLD is
negated. If the processor is driving data with BRDY on the 64-
bit data bus at the same time, the processor then drives 96 bits
simultaneously and ground-bounce spikes can occur.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...