5-1
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
5
Bus Interface
This chapter describes two closely related subjects, bus signals
(Sections 5.1 and 5.2) and the bus-cycle protocols implemented
with those signals (Sections 5.3 and 5.4). These sections
describe only the architectural characteristics and functions of
the signals and bus cycles. The processor data sheet defines
the setup and hold times for signals.
Throughout this chapter, unless otherwise stated, the term
clock refers to bus-clock (CLK) cycles, not processor-clock
cycles. The term cycle refers to bus cycles not clock cycles. The
terms asserted and negated mean that a signal is sampled
asserted or sampled negated by its target on the signal’s active
(typically rising) clock edge.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...