Signal Descriptions
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18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
latches any edge-triggered interrupt that may not be recog-
nized while EWBE is negated (FLUSH, SMI, NMI) and recog-
nizes them in priority order when EWBE is asserted.
If system logic implements memory-mapped I/O as non-cache-
able memory (the standard method), EWBE on the AMD-K5
processor has the same effect on writes to memory-mapped I/O
as does EWBE on the Pentium processor—neither processor
reorders reads ahead of writes.
For more details on the function of EWBE, see the following
sections:
■
BRDY—Page 5-41.
■
HITM—Page 5-72.
■
SMI—Page 5-116.
■
SMIACT—Page 5-121.
■
STPCLK—Page 5-122.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...