Signal Descriptions
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18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
The processor drives writebacks by asserting ADS and either
reusing the inquire cycle address (if AHOLD is held asserted
throughout the writeback) or driving the address itself (if
AHOLD is negated for the writeback, or if BOFF or HOLD was
used to obtain the bus). If AHOLD is held asserted throughout
an inquire cycle and a subsequent writeback, system logic
must latch the inquire cycle address when it asserts EADS and
use the latched copy during the writeback. By contrast, if sys-
tem logic always negates AHOLD before the writeback, the
processor drives the writeback address when it asserts ADS for
the writeback, and system logic need not latch a copy of the
inquire cycle address.
Inquire cycles can be driven while LOCK is asserted, if
AHOLD is used to obtain the bus for the inquire cycle. An
inquire cycle cannot hit a line involved in a locked operation.
Cached locations that are about to be accessed in locked opera-
tions are written back and invalidated before the locked opera-
tion occurs. If such an inquire cycle hits a modified location
that is different than the one involved in the locked operation,
the writeback is done in the middle of the locked operation,
between the two locked cycles, and LOCK is asserted during
the writeback. This is the only case in which another operation
can intervene in a locked operation. System logic must recog-
nize this case and know that the inquire cycle is snooping a dif-
ferent location than the one that is locked.
At the falling edge of RESET, the states of BRDYC and BUS-
CHK control the drive strength on the A21–A3 (not including
A31–A22), ADS, HITM, and W/R signals. The drive strength is
weak for all states of BRDYC and BUSCHK except when
BRDYC and BUSCHK are both Low, in which case the drive
strength is strong. The A31–A22 signals use the weak drive
strength at all times. See the data sheet for details.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...