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Bus Interface
AMD-K5 Processor Technical Reference Manual
18524C/0—Nov1996
writeback is pending when BOFF is negated, the writeback
takes precedence over the restarting of the aborted cycles in
the locked operation.
For purposes of interrupts and exceptions, locked operations
are treated by the processor as if the entire multi-cycle opera-
tion were a single instruction. Thus, interrupts and exceptions
are not recognized during locked operations. The processor
samples BUSCHK if it is asserted with any BRDY of a locked
operation, but the processor does not generate an enabled
machine check interrupt for the BUSCHK until after the
locked operation completes, and thus the exception will not
intervene in the locked operation. If an edge-triggered inter-
rupt (FLUSH, SMI, INIT, or NMI) is asserted during a locked
operation, the interrupt is latched and recognized after the
locked operation completes, even if the interrupt signal is not
held asserted until the locked operation completes.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...