Bus Cycle Timing
5-151
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
(rather than BRDY) is asserted. KEN and WB/WT are validated
by either NA or BRDY, whichever comes first. NA will not gen-
erate a pipelined cycle in the event that there are no pending
internal cycles.
Figure 5-6. Burst Reads
CLK
A31–A3
ADS
BE7–BE0
BRDY
BREQ
CACHE
D/C
D63–D0
KEN
M/IO
PWT
W/R
WB/WT
CLK
Read
Read
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...