Signal Descriptions
5-17
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
cache lines back to memory, an in-progress writeback will be
aborted, but it will be restarted after BOFF is negated, and the
FLUSH operation will then continue; any writebacks that com-
pleted before BOFF was asserted are not affected.
5.1.4
Bus Signal Compatibility with Pentium Processor
The differences in bus signal functions between the AMD-K5
and Pentium processors are described in Section A.1 on page
A-2.
5.2
Signal Descriptions
The following pages describe each signal in detail. The bus
cycle protocols that use these signals are described in Section
5.3 on page 5-136. Chapter 6 describes the context in which the
SMM and clock-control signals are used, and Chapter 7 does
the same for the test signals.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...