Signal Descriptions
5-89
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
5.2.34
KEN (External Cache Enable)
Input
Summary
System logic overrides the cacheability of read cycles with
KEN. If KEN is negated during a read cycle, the data returned
to the processor will not be cached. If KEN is asserted at that
time, cacheability and the MESI state of cached lines depends
on the states of the CACHE and PWT outputs and the WB/WT
input.
Sampled
The processor samples KEN in the same clock as the first
BRDY of the read cycle or NA, whichever comes first.
KEN is sampled only during memory reads in the normal oper-
ating modes (Real, Protected, and Virtual-8086) and in SMM.
KEN is not sampled during memory writes, inquire cycles, I/O
cycles, locked cycles, special bus cycles, or interrupt acknowl-
edge operations; during the Shutdown, Halt, Stop Grant, or
Stop Clock states; or while BOFF, HLDA, RESET, INIT, or
PRDY is asserted. While AHOLD is asserted, KEN is sampled
only to complete a bus cycle already begun before the asser-
tion of AHOLD.
Details
System logic typically maintains a specification of address
cacheability in external registers that are written by BIOS at
boot time. The BIOS does this by knowing or determining the
address ranges of memory-mapped I/O ports and other loca-
tions that should be noncacheable. For example, video and net-
work boards are normally mapped by BIOS to the high-memory
area between 640 Kbyte and 1 Mbyte, an area that is non-
cacheable for both functional and security reasons. (The pro-
cessor would not be able to detect changes in the state of mem-
ory-mapped network or semaphore I/O ports that are cached,
and video frames written to a writeback cache would not be
visible on a display.)
In Protected mode (paging enabled), the operating system can
map linear addresses to physical addresses using pages that it
knows to be cacheable or non-cacheable. But in non-paging
modes, the operating system has no control over cacheability
and the external cacheability registers are the only available
mechanism for determining whether an address is cacheable or
non-cacheable.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...