Features
1-3
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
■
High-Performance Cache and TLBs
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16-Kbyte instruction cache supports split-line access
•
8-Kbyte, dual-ported data cache with MESI cache coher-
ency protocol
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Dual-tagged (both linear and physical tags)
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Inquire cycles run in parallel with program cache access
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4-Kbyte TLB (128 entries) and 4-Mbyte TLB (4 entries)
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Extended Features
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Control Register 4 (CR4)
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CMPXCHG8B instruction
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CPUID instruction
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Time stamp counter (TSC)
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Machine-Specific Registers (MSRs)
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4-Mbyte page size
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Global pages held in TLB during flushes
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Low Power
•
Static, 3.3-V design
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System Management Mode (SMM) with I/O trapping
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Low-power halt and stop-clock states
•
Compatible with U.S. Department of Energy’s Energy
Star program
•
Compatible with Microsoft Advanced Power Manage-
ment specification
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Extensive Test and Debug Features
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Two built-in self-test (BIST) modes
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Output-Float Test mode
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Cache and TLB testing (tags and data)
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Debug registers, with I/O breakpoint extension
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Branch tracing
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Functional-redundancy checking
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IEEE 1149.1-1990 Test Access Port (TAP) and JTAG
boundary-scan testing
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Hardware Debug Tool (HDT)
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...