Memory Management Unit (MMU)
2-29
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
the TLB reload involves a write to memory to set the PDE
Accessed or Dirty bit, a hit during the physical-tag snoop
causes the cache line to be invalidated.
Details on software configuration for 4-Mbyte paging are given
in Section 3.1.2 on page 3-5. The global-page option is
described in Section 3.1.3 on page 3-9. Details on the TLB stor-
age formats and their testing are given in Section 7.4 on page
7-7.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...