Signal Descriptions
5-51
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
CACHE is not asserted for the following types of memory reads
(M/IO = 1):
■
Locked reads (that is, while LOCK is asserted)
■
TLB reads
■
Any read with PCD asserted (PCD is a factor in determining
the state of CACHE)
On the 486 processor, by comparison, the CACHE output does
not exist, but the BLAST output (in conjunction with KEN)
serves to determine cacheability. Although bursts are typically
four 32-bit transfers on the 486 processor, they can be longer
with narrower-width memories.
Table 5-9. MESI-State Transitions for Reads
Signal or Event
Result of Cache Lookup
Read Miss
Read Hit
shared
exclusive
modified
CACHE, PCD
1
1
—
0
0
0
—
—
—
KEN
—
1
0
0
0
—
—
—
PWT
—
—
1
—
0
—
—
—
WB/WT
—
—
—
0
1
—
—
—
Cache Line Fill
(32 bytes)
no
no
yes
yes
yes
no
no
no
State After Read
2
—
—
shared
shared
exclusive
shared
exclusive
modified
Notes:
— Don’t care or not applicable.
1. The PCD bit is one determinant of the state of CACHE.
2. Transition occurs after any line fill. Lines in “shared” MESI state are said to be in “writethrough” state. Those in “exclusive” or “mod-
ified” MESI states are said to be in “writeback” state.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...