Boundary-Scan Test Access Port (TAP)
7-19
18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
Errors detected by the checker are reported on the IERR out-
put of the checker. If a mismatch occurs on such a comparison,
the checker asserts IERR for one clock, two clocks after the
detection of the error. Both the master and the checker con-
tinue running the checking program after an error occurs. No
action other than the assertion of IERR is taken by the proces-
sor. On the AMD-K5 processor, the IERR output is reserved
solely for functional-redundancy checking. No other errors are
reported on that output.
Functional-redundancy checking is typically implemented on
single-processor, fault-monitoring systems (which actually
have two processors). The master processor runs the opera-
tional programs and the checker processor is dedicated
entirely to constant checking. In this arrangement, the test of
accurate operation consists solely of reporting one or more
errors. The particular type of error or the instruction causing
an error is not reported. The arrangement works because the
processor is entirely deterministic. Speculative prefetching,
speculative execution, and cache replacement all occur in
identical ways and at identical times on both processors if their
signals are tied together so that they run the same program.
The Functional-Redundancy Checking mode can only be
exited by the assertion of RESET. Functional-redundancy
checking cannot be performed in the Hardware Debug Tool
(HDT) mode. The assertion of FRCMC is not recognized while
PRDY is asserted.
7.8
Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP)—originally pro-
posed by the Joint European Test Action Group (JETAG) and,
later, Joint Test Action Group (JTAG)—is an IEEE standard
that defines synchronous scanning test methods for complex
logic circuits, such as boards containing a microprocessor. The
AMD-K5 processor supports the full TAP standard defined in
the IEEE Standard Test Access Port and Boundary-Scan Architec-
ture (IEEE 1149.1-1990) specification.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...