Bus Mastering Operations (including Snooping)
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18524C/0—Nov1996
AMD-K5 Processor Technical Reference Manual
as a miss. For ICACHE linefills, the AMD-K5 processor may
treat the snoop as a hit or a miss, because the speculative
nature of the linefills makes their cacheability dependent on
the code sequence and, therefore, unpredictable from an exter-
nal system point of view.
This difference applies to the AMD-K5 processor Model 0.
Model 1 of the AMD-K5 processor does not have the difference.
Comments
In treating the snoop as a hit, the AMD-K5 and Pentium proces-
sors assert the HIT pin and also cache the line as either shared
or invalid, depending on the state of the INV pin. The cycle
restarts after the deassertion of BOFF and AHOLD.
In treating the snoop as a miss, the AMD-K5 processor deas-
serts the HIT pin. The state of the line is determined based on
KEN, WB/WT, and PWT when the cycle is restarted after the
deassertion of BOFF and AHOLD.
The behavior of snoops to the linefill buffer before cacheabil-
ity is determined is described in Section A.3.1.
A.3.3
Snoop Before Write Hit to ICACHE Appears on Bus
If a write to a valid ICACHE line occurs and a snoop occurs to
the same line before the write appears on the bus, the Pentium
processor generates a snoop hit until the write is on the bus.
The AMD-K5 processor generates a snoop miss in the window
between when the cache is invalidated and the write appears
on the bus. The ICACHE line is invalidated in both processors
by the time the write appears on the bus.
A.3.4
Invalidations during a FLUSH/WBINVD
During a FLUSH/WBINVD between a line copyback and the
Flush Acknowledge cycle, a subsequent snoop to that line
reports a snoop hit modified and generates another copyback.
The Pentium processor invalidates lines as they are accessed
during FLUSH. The AMD-K5 processor invalidates all lines at
the end of a FLUSH.
Once FLUSH/WBINVD has completed, the entire cache is
invalid for both the AMD-K5 and Pentium processors.
Summary of Contents for AMD-K5
Page 1: ...AMD K5 Processor Technical Reference Manual TM...
Page 10: ...x AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 24: ...1 4 Overview AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 54: ...2 30 Internal Architecture AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 116: ...4 26 Performance AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 356: ...6 44 System Design AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 380: ...7 24 Test and Debug AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 396: ...A 16 AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...
Page 406: ...I 10 Index AMD K5 Processor Technical Reference Manual 18524C 0 Nov1996...