Intel Itanium 9010 Manual Download

Page: 1 / 108

Document Number: 314054-002

Dual-Core Intel

Itanium

Processor

9000 and 9100 Series

Dual-Core Intel

Itanium

Processor 1.6 GHz with 24 MB L3 Cache 9050

Dual-Core Intel

Itanium

Processor 1.6 GHz with 18 MB L3 Cache 9040

Dual-Core Intel

Itanium

Processor 1.6 GHz with 8 MB L3 Cache 9030

Dual-Core Intel

Itanium

Processor 1.42 GHz with 12 MB L3 Cache 9020

Dual-Core Intel

Itanium

Processor 1.4 GHz with 12 MB L3 Cache 9015

Intel

Itanium

Processor 1.6 GHz with 6 MB L3 Cache 9010

Dual-Core Intel® Itanium® Processor 1.66/1.6 GHz with 24 MB L3 Cache 9152
Dual-Core Intel

Itanium

Processor 1.66 GHz with 24 MB L3 Cache 9150M

Dual-Core Intel

Itanium

Processor 1.6 GHz with 24 MB L3 Cache 9150N

Dual-Core Intel

Itanium

Processor 1.66 GHz with 18 MB L3 Cache 9140M

Dual-Core Intel

Itanium

Processor 1.6 GHz with 18 MB L3 Cache 9140N

Dual-Core Intel

Itanium

Processor 1.42 GHz with 12 MB L3 Cache 9120N

Dual-Core Intel

Itanium

Processor 1.66 GHz with 8 MB L3 Cache 9130M

Intel

Itanium

Processor 1.6 GHz with 12 MB L3 Cache 9110N

Datasheet

October 2007

Summary of Contents for Itanium 9010

Page 1: ...Intel Itanium Processor 1 6 GHz with 6 MB L3 Cache 9010 Dual Core Intel Itanium Processor 1 66 1 6 GHz with 24 MB L3 Cache 9152 Dual Core Intel Itanium Processor 1 66 GHz with 24 MB L3 Cache 9150M Dual Core Intel Itanium Processor 1 6 GHz with 24 MB L3 Cache 9150N Dual Core Intel Itanium Processor 1 66 GHz with 18 MB L3 Cache 9140M Dual Core Intel Itanium Processor 1 6 GHz with 18 MB L3 Cache 9140...

Page 2: ...ity whatsoever for conflicts or incompatibilities arising from future changes to them The Dual Core Intel Itanium 9000 and 9100 series processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request Contact your local Intel sales office or your distributor to obtain the latest ...

Page 3: ...or 24 2 5 4 Reading Overshoot Undershoot Specification Tables 24 2 5 5 Determining if a System Meets the Overshoot Undershoot Specifications 25 2 5 6 Wired OR Signals 25 2 6 Voltage Regulator Connector Signals 27 2 7 System Bus Clock and Processor Clocking 31 2 8 Recommended Connections for Unused Pins 33 3 Pinout Specifications 35 4 Mechanical Specifications 65 4 1 Processor Package Dimensions 65...

Page 4: ... O 91 A 1 6 ATTR 3 0 I O 92 A 1 7 BCLKp BCLKn I 92 A 1 8 BE 7 0 I O 92 A 1 9 BERR I O 93 A 1 10 BINIT I O 94 A 1 11 BNR I O 94 A 1 12 BPM 5 0 I O 94 A 1 13 BPRI I 94 A 1 14 BR 0 I O and BR 3 1 I 94 A 1 15 BREQ 3 0 I O 95 A 1 16 CCL I O 96 A 1 17 CPUPRES O 96 A 1 18 D 127 0 I O 96 A 1 19 D C I O 96 A 1 20 DBSY I O 96 A 1 21 DBSY_C1 O 96 A 1 22 DBSY_C2 O 96 A 1 23 DEFER I 96 A 1 24 DEN I O 97 A 1 25...

Page 5: ...Bus Signal Waveform Exhibiting Overshoot Undershoot 23 2 4 Processors Power Tab Physical Layout 28 2 5 System Bus Reset and Configuration Timings for Cold Reset 31 2 6 System Bus Reset and Configuration Timings for Warm Reset 32 3 1 Dual Core Intel Itanium Processor 9000 and 9100 Series Pinout 35 4 1 Processor Package 66 4 2 Package Height and Pin Dimensions 67 4 3 Processor Package Mechanical Int...

Page 6: ... HIT HITM BNR TND BERR Overshoot Undershoot Tolerance for 533 MHz System Bus 27 2 18 VR Connector Signals 27 2 19 Power Connector Pinouts 28 2 20 Processors Core Voltage Identification Code VCORE and VCACHE 30 2 21 Connection for Unused Pins 33 2 22 TUNER1 TUNER3 Translation Table 34 3 1 Pin Signal Information Sorted by Pin Name 36 3 2 Pin Signal Information Sorted by Pin Location 50 4 1 Processor...

Page 7: ...nterconnect 95 A 4 BR0 I O BR1 BR2 BR3 Signals for 4P Rotating Interconnect 95 A 6 BR 3 0 Signals and Agent IDs 95 A 7 DID 9 0 Encoding 97 A 8 Extended Function Signals 98 A 9 Length of Data Transfers 100 A 10 Transaction Types Defined by REQa REQb Signals 102 A 11 STBp 7 0 and STBn 7 0 Associations 104 A 12 Output Signals 105 A 13 Input Signals 105 A 14 Input Output Signals Single Driver 106 A 15...

Page 8: ... Series Datasheet Revision History Document Number Revision Number Description Date 314054 002 Updated with 9100 series product information updated brand name from Itanium 2 to Itanium October 2007 314054 001 Initial release of the document July 2006 ...

Page 9: ...nce Integrated on die L3 cache of up to 24MB cache hints for L1 L2 and L3 caches for reduced memory latency 128 general and 128 floating point registers supporting register rotation Register stack engine for effective management of processor resources Support for predication and speculation Extensive RAS features for business critical applications Full SMBus compatibility Enhanced machine check ar...

Page 10: ...L3 cache 24 megabytes Hyper Threading Technology for increased performance Intel Virtualization Technology for improved virtualization Intel Cache Safe Technology for increased availability and 20 percent lower power consumption Dual Core Itanium based systems are available from leading OEMs worldwide and run popular 64 bit operating systems such as Microsoft Windows Server 2003 Linux from SuSE Re...

Page 11: ...units two load and two store units three branch units two extended precision floating point units and one additional single precision floating point unit per core The hardware employs dynamic prefetch branch prediction a register scoreboard and non blocking caches to optimize for compile time non determinism Three levels of on die cache minimize overall memory latency This includes up to a 24 MB L...

Page 12: ...than the supported configurations described above 1 4 Terminology In this document the processor refers to the Dual Core Intel Itanium processor 9000 and 9100 series processor unless otherwise indicated A symbol after a signal name refers to an active low signal This means that a signal is in the active state based on the name of the signal when driven to a low level For example when RESET is low ...

Page 13: ...documents Intel Itanium 2 Processor Specification Update Intel Itanium Architecture Software Developer s Manual Volume 1 Application Architecture Intel Itanium Architecture Software Developer s Manual Volume 2 System Architecture Intel Itanium Architecture Software Developer s Manual Volume 3 Instruction Set Reference Intel Itanium 2 Processor Reference Manual for Software Development and Optimiza...

Page 14: ...14 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Introduction ...

Page 15: ...tion in which case the termination is provided by external resistors connected to VCTERM AGTL inputs use differential receivers which require a reference signal VREF VREF is used by the receivers to determine if a signal is a logical 0 or a logical 1 The processor generates VREF on die thereby eliminating the need for an off chip reference voltage source 2 1 1 System Bus Power Pins VCTERM 1 2 V in...

Page 16: ...see the TERMA and TERMB pin description in Section 2 2 2 The HSTL clock signals are the differential clock inputs for the processor The SMBus signals and LVTTL power pod signals are driven using the 3 3 V CMOS logic levels listed in Table 2 8 and Table 2 9 respectively Table 2 1 Itanium Processor System Bus Signal Groups Group Name Signals AGTL Input Signals BPRI BR 3 1 DEFER GSEQ ID 9 0 IDS RESET...

Page 17: ... die termination resistance On die termination mode will only be selected if the TERMA and TERMB pins are terminated as indicated above The TUNER3 pin will not be required for the majority of platforms supporting the Dual Core Intel Itanium processor 9000 and 9100 series The TUNER3 pin is used only in the case where A 21 17 are driven to all zeros or all ones during the configuration cycles at res...

Page 18: ...V 2 2 Vcache typical is 1 025 V Vfixed PS Vfixed from the Voltage Regulator All 1 25 20 mV 1 25 1 25 20 mV V VCTERM Termination Voltage All 1 2 1 5 1 2 1 2 1 5 V RTERM Recommended Termination Resistance All 45 15 45 45 15 Ohm 3 3 The processor system bus is terminated at each end of the system bus The processor supports both on die and off die termination which is selected by the TERMA and TERMB p...

Page 19: ...on die termination to a 45 15 resistor measured at VOL IL Leakage Current All 100 µA 5 5 At 1 2 V 1 5 VCTERM minimum Vpin VCTERM maximum CAGTL AGTL Pad Capacitance All 2 pF 6 6 Total of I O buffer with ESD structure and processor parasitics if applicable Capacitance values guaranteed by design for all AGTL buffers Table 2 5 Power Good Signal DC Specifications Symbol Parameter Minimum Maximum Unit ...

Page 20: ...fied for IOL2 applies only to THRMALERT which is an open drain signal ILI Input Leakage Current 10 µA ILO Output Leakage Current 10 µA Table 2 9 LVTTL Signal DC Specifications Symbol Parameter Minimum Maximum Unit Notes VIL Input Low Voltage 0 8 V VIH Input High Voltage 2 0 3 63 V VOL Output Low Voltage 0 4 V VOH Output High Voltage 2 4 V Table 2 10 System Bus Clock Differential HSTL AC Specificat...

Page 21: ...ing 7 The measurement is taken at 40 60 of the signal and extrapolated to 20 80 Table 2 11 SMBus AC Specifications Symbol Parameter Minimum Maximum Unit Notes fSMSC SMSC Clock Frequency 100 kHz TSMSC SMSC Clock Period 10 µs thigh SMSC Clock High Time 4 0 µs 1 Notes 1 Please refer to Figure 2 2 for the Standard Microsystems Corporation SMSC clock waveform tlow SMSC Clock Low Time 4 7 µs 1 trise SMS...

Page 22: ...ngs Symbol Parameter Minimum Maximum Unit Notes Tstorage Processor Storage Temperature 10 45 C 1 Notes 1 Storage temperature is temperature in which the processor can be stored for up to one year Tshipping Processor Shipping Temperature 45 75 C 2 2 Shipping temperature is temperature in which the processor can be shipped for up to 24 hours Vcore Any Vcore Voltage with Respect to GND 0 3 1 55 V Vca...

Page 23: ... Overshoot Undershoot Magnitude Magnitude describes the maximum potential difference between a signal and its voltage reference level For the processor both are referenced to GND as shown in Figure 2 3 It is important to note that overshoot and undershoot conditions are separate and their impact must be determined independently Overshoot undershoot magnitude levels must observe the absolute maximu...

Page 24: ...of all others meaning that the pulse duration reflects the existence of overshoot undershoot events of that magnitude ONLY A platform with an overshoot undershoot that just meets the pulse duration for a specific magnitude where the AF 1 means that there can be no other overshoot undershoot events even of lesser magnitude if AF 1 then the event occurs at all times and no other events can occur Not...

Page 25: ...events meet the specifications measured time specifications in the table where AF 1 then the system passes 2 5 6 Wired OR Signals To ensure platform compatibility between the processors system bus signals must meet certain overshoot and undershoot requirements The system bus wired OR signals BINIT HIT HITM BNR TND BERR have the same absolute overshoot and undershoot specification as the Source Syn...

Page 26: ... HIT HITM BNR TND BERR Overshoot Undershoot Tolerance for 400 MHz System Bus Absolute Maximum V Pulse Duration ns Over shoot Under shoot AF 11 Notes 1 Activity Factor 1 means signal toggles every 10 ns AF 0 75 AF 0 5 AF 0 25 AF 0 1 AF 0 05 AF 0 01 1 65 0 45 0 0166 0 0192 0 0306 0 0614 0 1539 0 3067 1 5374 1 6 0 4 0 0506 0 0674 0 1017 0 2032 0 5090 1 0213 5 1 55 0 35 0 1659 0 2216 0 3342 0 6676 1 6...

Page 27: ...nal Group BINIT HIT HITM BNR TND BERR Overshoot Undershoot Tolerance for 533 MHz System Bus Absolute Maximum V Pulse Duration ns Over shoot Under shoot AF 11 Notes 1 Activity Factor 1 means signal toggles every 7 5 ns AF 0 75 AF 0 5 AF 0 25 AF 0 1 AF 0 05 AF 0 01 1 65 0 45 0 01248 0 0144 0 0230 0 0461 0 1155 0 2301 1 1530 1 6 0 4 0 0380 0 0507 0 0763 0 1522 0 3814 0 7627 3 75 1 55 0 35 0 1250 0 16...

Page 28: ...inouts Sheet 1 of 2 Power Tab VR Pads Description A1 C1 GND L1 N1 GND A2 PPODGD B2 CPUPRES D1 K1 C2 D2 E2 Vfixed H2 N2 Vfixed A3 Vid_valid B3 Vid_core 0 C3 Vid_core 1 D3 Vid_core 2 E3 Vid_core 3 F3 Vid_core 4 G3 Vid_core 5 H3 Vid_cache 0 J3 Vid_cache 1 K3 Vid_cache 2 L3 Vid_cache 3 M3 Vid_cache 4 N3 Vid_cache 5 A4 N4 GND A5 N5 Vcache A6 N6 GND A7 N7 Vcore A8 N8 GND A9 N9 Vcore ...

Page 29: ...e controlled by the processor A10 N10 GND A11 N11 Vcore A12 N12 GND A13 N13 Vcore A14 N14 GND A15 N15 Vcore A16 N16 GND A17 N17 Vcore A18 N18 GND A19 N19 Vcore A20 N20 GND A21 N21 Vcore A22 N22 GND A23 N23 Vcore A24 N24 GND A25 N25 Vcore A26 N26 GND A27 N27 Vcache A28 N28 GND A29 Vcache_sense B29 Gnd_sense C29 Vcore_sense D29 Vfixed_sense K29 GND L29 Reserved M29 Reserved N29 OUTEN A30 D30 GND L30...

Page 30: ...0 1 1 1 0 8125 1 1 0 1 1 0 1 2 0 1 0 1 1 0 0 8 1 1 0 1 0 1 1 1875 0 1 0 1 0 1 0 7875 1 1 0 1 0 0 1 175 0 1 0 1 0 0 0 775 1 1 0 0 1 1 1 1625 0 1 0 0 1 1 0 7625 1 1 0 0 1 0 1 15 0 1 0 0 1 0 0 75 1 1 0 0 0 1 1 1375 0 1 0 0 0 1 0 7375 1 1 0 0 0 0 1 125 0 1 0 0 0 0 0 725 1 0 1 1 1 1 1 1125 0 0 1 1 1 1 0 7125 1 0 1 1 1 0 1 1 0 0 1 1 1 0 0 7 1 0 1 1 0 1 1 0875 0 0 1 1 0 1 0 6875 1 0 1 1 0 0 1 075 0 0 1 1...

Page 31: ...millisecond minimum After RESET is deasserted all the configuration including pins A 21 17 must remain valid for 2 BCLKs minimum to 3 BCLKs maximum BCLK is shown as a time reference to the BCLK period It is not a requirement that this is BCLKn or BCLKp signal Configuration signals other than A 21 17 must be asserted 4 BCLKs prior to the deasserted edge of RESET and must remain valid for 2 BCLKs mi...

Page 32: ...t that this is BCLKn or BCLKp signal Configuration signals other than A 21 17 must be asserted four BCLKs prior to the deasserted edge of RESET and must remain valid for two BCLKs minimum to three BCLKs maximum after the deasserted edge of RESET Figure 2 6 outlines the timing relationship between the configuration pins RESET and PWRGOOD for warm reset Figure 2 6 System Bus Reset and Configuration ...

Page 33: ...gnals SBSY 0 1 DBSY 0 1 and DRDY 0 1 may be left as N C if not used on platform HSTL Clock Signals Must be used All Power Signals Must be used PWRGOOD Must be used TAP Signals TCK L 1 3 TRST L 1 3 3 Can be No Connect or connected to VCTERM via a 100ohm or 150 ohm resistor TDI H 1 3 TDO H 1 3 TMS H 1 3 System Management Signals 3 3V GND SMA 2 0 N C SMSC N C SMSD N C SMWP N C THRMALERT H 1 4 4 THRMA...

Page 34: ...ical Specifications Table 2 22 TUNER1 TUNER3 Translation Table A 21 17 1 Notes 1 0 VCTERM 1 GND TUNER12 2 0 Resistor not present 1 Resistor present TUNER32 System Bus MHz Slew Rate V ns 0 0 0 667 1 7 0 0 1 533 1 4 0 1 N A 400 0 8 1 0 0 667 1 92 1 0 1 533 1 7 1 1 N A 400 0 82 ...

Page 35: ... Y L O C K G S E Q D E F E R A 3 4 A 3 1 V C T E R M D 9 4 D 5 9 D 8 7 V C T E R M D 8 4 N C V C T E R M D 7 5 D 6 8 V C T E R M D 6 5 G N D N C V C T E R M G N D G N D T N D G N D B IN IT G N D G N D A 2 8 G N D D 9 2 G N D D 9 1 G N D D 8 1 G N D D 7 8 G N D D 7 1 G N D D 6 7 G N D N C G N D S M A 2 B R E Q 0 B R E Q 1 N C N C A 3 6 A 3 8 D E P 1 1 V C T E R M D 9 3 S T B P 5 V C T E R M D 8 3 G...

Page 36: ... OUT A010 AA10 BE2 V04 IN OUT A011 AA11 BE3 AA05 IN OUT A012 AA12 BE4 W05 IN OUT A013 AA13 BE5 Y04 IN OUT A014 AA14 BE6 W07 IN OUT A015 AA15 BE7 V08 IN OUT A016 AA16 DID0 U13 IN OUT A017 AA17 DID1 Y08 IN OUT A018 AA18 DID2 U09 IN OUT A019 AA19 DID3 V12 IN OUT A020 AA20 DID4 V10 IN OUT A021 AA21 DID5 W09 IN OUT A022 AA22 DID6 W13 IN OUT A023 AA23 DID7 AA11 IN OUT A024 AA24 DID8 Y10 IN OUT A025 AA25...

Page 37: ... BNR U17 IN OUT BPM0 BPM0 AD22 IN OUT BPM1 BPM1 AC25 IN OUT BPM2 BPM2 AE23 IN OUT BPM3 BPM3 AC23 IN OUT BPM4 BPM4 AD24 IN OUT BPM5 BPM5 AB24 IN OUT BPRI BPRI AE19 IN BR0 BREQ0 AF16 IN OUT BR1 BREQ1 AD16 IN BR2 BREQ2 AB18 IN BR3 BREQ3 AF18 IN CPUPRES CPUPRES AG15 OUT Power pod signal D000 D00 C07 IN OUT D001 D01 E03 IN OUT D002 D02 C05 IN OUT D003 D03 D04 IN OUT D004 D04 D02 IN OUT D005 D05 D06 IN ...

Page 38: ... D032 D32 H10 IN OUT D033 D33 C11 IN OUT D034 D34 D10 IN OUT D035 D35 C09 IN OUT D036 D36 D12 IN OUT D037 D37 D08 IN OUT D038 D38 G09 IN OUT D039 D39 E13 IN OUT D040 D40 E09 IN OUT D041 D41 G11 IN OUT D042 D42 H08 IN OUT D043 D43 G13 IN OUT D044 D44 F12 IN OUT D045 D45 F08 IN OUT D046 D46 H12 IN OUT D047 D47 J13 IN OUT D048 D48 M08 IN OUT D049 D49 K08 IN OUT D050 D50 K10 IN OUT D051 D51 M12 IN OUT...

Page 39: ...D076 D76 H16 IN OUT D077 D77 H18 IN OUT D078 D78 J15 IN OUT D079 D79 G19 IN OUT D080 D80 K18 IN OUT D081 D81 L15 IN OUT D082 D82 L19 IN OUT D083 D83 K16 IN OUT D084 D84 M14 IN OUT D085 D85 N19 IN OUT D086 D86 M18 IN OUT D087 D87 P14 IN OUT D088 D88 L17 IN OUT D089 D89 R17 IN OUT D090 D90 R19 IN OUT D091 D91 N15 IN OUT D092 D92 R15 IN OUT D093 D93 P16 IN OUT D094 D94 T14 IN OUT D095 D95 P18 IN OUT ...

Page 40: ...IN OUT D121 D121 R25 IN OUT D122 D122 P20 IN OUT D123 D123 T24 IN OUT D124 D124 R21 IN OUT D125 D125 P22 IN OUT D126 D126 R23 IN OUT D127 D127 N21 IN OUT DBSY DBSY AC09 IN OUT DBSY0 DBSY_C1 AA09 OUT DBSY1 DBSY_C2 AA19 OUT DEFER DEFER AB14 IN DEP00 DEP0 J07 IN OUT DEP01 DEP1 J05 IN OUT DEP02 DEP2 T06 IN OUT DEP03 DEP3 T04 IN OUT DEP04 DEP4 J09 IN OUT DEP05 DEP5 J11 IN OUT DEP06 DEP6 T08 IN OUT DEP0...

Page 41: ...ND GND AA02 IN GND GND AA20 IN GND GND AA24 IN GND GND AB01 IN GND GND AB03 IN GND GND AB05 IN GND GND AB07 IN GND GND AB09 IN GND GND AB11 IN GND GND AB13 IN GND GND AB15 IN GND GND AB17 IN GND GND AB19 IN GND GND AB21 IN GND GND AB23 IN GND GND AB25 IN GND GND AC02 IN GND GND AC24 IN GND GND AD01 IN GND GND AD03 IN GND GND AD05 IN GND GND AD07 IN GND GND AD09 IN GND GND AD11 IN GND GND AD13 IN G...

Page 42: ... AG04 IN GND GND AG06 IN GND GND AG08 IN GND GND AG10 IN GND GND AG12 IN GND GND AG14 IN GND GND AG16 IN GND GND AG18 IN GND GND AG20 IN GND GND AG22 IN GND GND AG24 IN GND GND AH01 IN GND GND B03 IN GND GND B05 IN GND GND B07 IN GND GND B09 IN GND GND B10 IN GND GND B11 IN GND GND B13 IN GND GND B15 IN GND GND B17 IN GND GND B19 IN GND GND B21 IN GND GND B23 IN GND GND B25 IN GND GND C02 IN GND G...

Page 43: ...04 IN GND GND E08 IN GND GND E12 IN GND GND E16 IN GND GND E20 IN GND GND E24 IN GND GND F01 IN GND GND F03 IN GND GND F05 IN GND GND F07 IN GND GND F09 IN GND GND F11 IN GND GND F13 IN GND GND F15 IN GND GND F17 IN GND GND F19 IN GND GND F21 IN GND GND F23 IN GND GND F25 IN GND GND G02 IN GND GND H03 IN GND GND H05 IN GND GND H07 IN GND GND H09 IN GND GND H11 IN GND GND H13 IN GND GND H15 IN GND ...

Page 44: ...13 IN GND GND K15 IN GND GND K17 IN GND GND K19 IN GND GND K21 IN GND GND K23 IN GND GND K25 IN GND GND L02 IN GND GND M01 IN GND GND M03 IN GND GND M05 IN GND GND M07 IN GND GND M09 IN GND GND M11 IN GND GND M13 IN GND GND M15 IN GND GND M17 IN GND GND M19 IN GND GND M21 IN GND GND M23 IN GND GND M25 IN GND GND N04 IN GND GND N20 IN GND GND N24 IN GND GND P01 IN GND GND P03 IN GND GND P05 IN GND ...

Page 45: ...13 IN GND GND T15 IN GND GND T17 IN GND GND T19 IN GND GND T21 IN GND GND T23 IN GND GND T25 IN GND GND U04 IN GND GND U20 IN GND GND U24 IN GND GND V01 IN GND GND V03 IN GND GND V05 IN GND GND V07 IN GND GND V09 IN GND GND V11 IN GND GND V13 IN GND GND V15 IN GND GND V17 IN GND GND V19 IN GND GND V21 IN GND GND V23 IN GND GND V25 IN GND GND W02 IN GND GND Y01 IN GND GND Y03 IN GND GND Y05 IN GND ...

Page 46: ...C03 IN ID3 IDA3 IDB3 AA03 IN ID4 IDA4 IDB4 AD04 IN ID5 IDA5 IDB5 AB04 IN ID6 IDA6 IDB6 AE05 IN ID7 IDA7 IDB7 AC05 IN ID8 IDA8 IDB8 AD06 IN ID9 IDA9 IDB9 AB06 IN IDS IDS AC07 IN IGNNE IGNNE AG23 N C INIT INIT AF08 IN LINT0 INT AF22 IN LINT1 NMI AF24 IN LOCK LOCK AE15 N C N C A04 N C AB16 N C AC17 N C AC21 N C AD18 N C AE17 N C AG05 N C AG11 N C AG17 N C AG19 N C AG21 N C AH05 N C AH11 N C AH17 N C ...

Page 47: ...Q3 ASZ0 DSZ0 AE11 IN OUT REQ4 ASZ1 DSZ1 AF12 IN OUT REQ5 REQ5 AD12 IN OUT RESET RESET AD20 IN RP RP AC13 IN OUT RS0 RS0 AE07 IN RS1 RS1 AD08 IN RS2 RS2 AB08 IN RSP RSP AF06 IN SBSY SBSY AE13 IN OUT SBSY0 SBSY_C1 AA13 OUT SBSY1 SBSY_C2 AC19 OUT SMA0 SMA0 B18 IN SMBus signal SMA1 SMA1 A17 IN SMBus signal SMA2 SMA2 A15 IN SMBus signal SMSC SMSC B24 IN SMBus signal SMSD SMSD B22 IN OUT SMBus signal SM...

Page 48: ...HRMTRIP THRMTRIP AG25 OUT THRMALERT THRMALERT A07 OUT TMS TMS AH09 IN JTAG TND TND AC15 IN OUT TRDY TRDY AF14 IN TRST TRST AE21 IN JTAG TUNER 1 TUNER 1 AH03 IN TUNER 2 TUNER 2 AG03 IN TUNER 3 TUNER 3 B08 IN VCCMON VCCMON A11 N C VCTERM VCTERM A02 IN VCTERM VCTERM A06 IN VCTERM VCTERM A10 IN VCTERM VCTERM A14 IN VCTERM VCTERM A18 IN VCTERM VCTERM A22 IN VCTERM VCTERM A25 IN VCTERM VCTERM C01 IN VCT...

Page 49: ...L01 IN VCTERM VCTERM L04 IN VCTERM VCTERM L08 IN VCTERM VCTERM L12 IN VCTERM VCTERM L16 IN VCTERM VCTERM L20 IN VCTERM VCTERM L24 IN VCTERM VCTERM N02 IN VCTERM VCTERM N06 IN VCTERM VCTERM N10 IN VCTERM VCTERM N14 IN VCTERM VCTERM N18 IN VCTERM VCTERM N22 IN VCTERM VCTERM R01 IN VCTERM VCTERM R04 IN VCTERM VCTERM R08 IN VCTERM VCTERM R12 IN VCTERM VCTERM R16 IN VCTERM VCTERM R20 IN VCTERM VCTERM R...

Page 50: ...CTERM A10 IN VCCMON VCCMON A11 N C GND GND A13 IN VCTERM VCTERM A14 IN SMA2 SMA2 A15 IN SMBus signal GND GND A16 IN SMA1 SMA1 A17 IN SMBus signal VCTERM VCTERM A18 IN GND GND A19 IN GND GND A20 IN SMWP SMWP A21 IN SMBus signal VCTERM VCTERM A22 IN GND GND A23 IN GND GND A24 IN VCTERM VCTERM A25 IN 3 3V B02 IN SMBus supply voltage GND GND B03 IN N C B04 GND GND B05 IN N C B06 GND GND B07 IN Tuner 3...

Page 51: ...C08 IN D035 D35 C09 IN OUT GND GND C10 IN D033 D33 C11 IN OUT VCTERM VCTERM C12 IN N C C13 GND GND C14 IN N C C15 VCTERM VCTERM C16 IN D073 D73 C17 IN OUT GND GND C18 IN D070 D70 C19 IN OUT VCTERM VCTERM C20 IN D099 D99 C21 IN OUT GND GND C22 IN D097 D97 C23 IN OUT VCTERM VCTERM C24 IN N C C25 GND GND D01 IN D004 D04 D02 IN OUT GND GND D03 IN D003 D03 D04 IN OUT GND GND D05 IN D005 D05 D06 IN OUT ...

Page 52: ...E05 IN OUT VCTERM VCTERM E06 IN D010 D10 E07 IN OUT GND GND E08 IN D040 D40 E09 IN OUT VCTERM VCTERM E10 IN STBP2 STBP2 E11 IN OUT GND GND E12 IN D039 D39 E13 IN OUT VCTERM VCTERM E14 IN D067 D67 E15 IN OUT GND GND E16 IN STBP4 STBP4 E17 IN OUT VCTERM VCTERM E18 IN D074 D74 E19 IN OUT GND GND E20 IN D096 D96 E21 IN OUT VCTERM VCTERM E22 IN STBP6 STBP6 E23 IN OUT GND GND E24 IN D100 D100 E25 IN OUT...

Page 53: ...IN OUT GND GND F25 IN VCTERM VCTERM G01 IN GND GND G02 IN D014 D14 G03 IN OUT VCTERM VCTERM G04 IN D008 D08 G05 IN OUT D015 D15 G07 IN OUT VCTERM VCTERM G08 IN D038 D38 G09 IN OUT D041 D41 G11 IN OUT VCTERM VCTERM G12 IN D043 D43 G13 IN OUT D071 D71 G15 IN OUT VCTERM VCTERM G16 IN D072 D72 G17 IN OUT D079 D79 G19 IN OUT VCTERM VCTERM G20 IN D101 D101 G21 IN OUT D108 D108 G23 IN OUT VCTERM VCTERM G...

Page 54: ...N OUT GND GND H25 IN GND GND J01 IN VCTERM VCTERM J02 IN D013 D13 J03 IN OUT GND GND J04 IN DEP01 DEP1 J05 IN OUT VCTERM VCTERM J06 IN DEP00 DEP0 J07 IN OUT GND GND J08 IN DEP04 DEP4 J09 IN OUT VCTERM VCTERM J10 IN DEP05 DEP5 J11 IN OUT GND GND J12 IN D047 D47 J13 IN OUT VCTERM VCTERM J14 IN D078 D78 J15 IN OUT GND GND J16 IN DEP09 DEP9 J17 IN OUT VCTERM VCTERM J18 IN DEP08 DEP8 J19 IN OUT GND GND...

Page 55: ...K20 IN OUT GND GND K21 IN D114 D114 K22 IN OUT GND GND K23 IN N C K24 GND GND K25 IN VCTERM VCTERM L01 IN GND GND L02 IN D017 D17 L03 IN OUT VCTERM VCTERM L04 IN D019 D19 L05 IN OUT D021 D21 L07 IN OUT VCTERM VCTERM L08 IN D053 D53 L09 IN OUT D056 D56 L11 IN OUT VCTERM VCTERM L12 IN D052 D52 L13 IN OUT D081 D81 L15 IN OUT VCTERM VCTERM L16 IN D088 D88 L17 IN OUT D082 D82 L19 IN OUT VCTERM VCTERM L...

Page 56: ...N OUT GND GND M19 IN D118 D118 M20 IN OUT GND GND M21 IN STBP7 STBP7 M22 IN OUT GND GND M23 IN D115 D115 M24 IN OUT GND GND M25 IN VCTERM VCTERM N02 IN D023 D23 N03 IN OUT GND GND N04 IN STBN1 STBN1 N05 IN OUT VCTERM VCTERM N06 IN D022 D22 N07 IN OUT D058 D58 N09 IN OUT VCTERM VCTERM N10 IN STBN3 STBN3 N11 IN OUT D055 D55 N13 IN OUT VCTERM VCTERM N14 IN D091 D91 N15 IN OUT STBN5 STBN5 N17 IN OUT V...

Page 57: ...6 IN OUT GND GND P17 IN D095 D95 P18 IN OUT GND GND P19 IN D122 D122 P20 IN OUT GND GND P21 IN D125 D125 P22 IN OUT GND GND P23 IN D120 D120 P24 IN OUT GND GND P25 IN VCTERM VCTERM R01 IN GND GND R02 IN D025 D25 R03 IN OUT VCTERM VCTERM R04 IN D029 D29 R05 IN OUT D031 D31 R07 IN OUT VCTERM VCTERM R08 IN D063 D63 R09 IN OUT D060 D60 R11 IN OUT VCTERM VCTERM R12 IN D059 D59 R13 IN OUT D092 D92 R15 I...

Page 58: ...DEP11 DEP11 T16 IN OUT GND GND T17 IN DEP10 DEP10 T18 IN OUT GND GND T19 IN DEP14 DEP14 T20 IN OUT GND GND T21 IN DEP15 DEP15 T22 IN OUT GND GND T23 IN D123 D123 T24 IN OUT GND GND T25 IN VCTERM VCTERM U02 IN A005 AA05 EXF2 U03 IN OUT GND GND U04 IN N C U05 VCTERM VCTERM U06 IN A009 AA09 BE1 U07 IN OUT A018 AA18 DID2 U09 IN OUT VCTERM VCTERM U10 IN N C U11 A016 AA16 DID0 U13 IN OUT VCTERM VCTERM U...

Page 59: ... IN OUT GND GND V15 IN A038 AA38 AB38 V16 IN OUT GND GND V17 IN A029 AA29 xTPRValue2 V18 IN OUT GND GND V19 IN A045 AA45 AB45 V20 IN OUT GND GND V21 IN A047 AA47 AB47 V22 IN OUT GND GND V23 IN A040 AA40 AB40 V24 IN OUT GND GND V25 IN GND GND W02 IN A006 AA06 EXF3 W03 IN OUT A012 AA12 BE4 W05 IN OUT A014 AA14 BE6 W07 IN OUT A021 AA21 DID5 W09 IN OUT A026 AA26 AB26 W11 IN OUT A022 AA22 DID6 W13 IN O...

Page 60: ...Y19 IN A039 AA39 AB39 Y20 IN OUT GND GND Y21 IN A049 AA49 AB49 Y22 IN OUT GND GND Y23 IN A043 AA43 AB43 Y24 IN OUT GND GND Y25 IN GND GND AA02 IN ID3 IDA3 IDB3 AA03 IN A011 AA11 BE3 AA05 IN OUT DRDY0 DRDY_C1 AA07 OUT DBSY0 DBSY_C1 AA09 OUT A023 AA23 DID7 AA11 IN OUT SBSY0 SBSY_C1 AA13 OUT BINIT BINIT AA15 IN OUT A033 AA33 ATTR1 AA17 IN OUT DBSY1 DBSY_C2 AA19 OUT GND GND AA20 IN DRDY1 DRDY_C2 AA21 ...

Page 61: ...D GND AB23 IN BPM5 BPM5 AB24 IN OUT GND GND AB25 IN GND GND AC02 IN ID2 IDA2 DHIT AC03 IN ID7 IDA7 IDB7 AC05 IN IDS IDS AC07 IN DBSY DBSY AC09 IN OUT DRDY DRDY AC11 IN OUT RP RP AC13 IN OUT TND TND AC15 IN OUT N C AC17 SBSY1 SBSY_C2 AC19 OUT N C AC21 BPM3 BPM3 AC23 IN OUT GND GND AC24 IN BPM1 BPM1 AC25 IN OUT GND GND AD01 IN ID0 IDA0 IP0 AD02 IN GND GND AD03 IN ID4 IDA4 IDB4 AD04 IN GND GND AD05 I...

Page 62: ...05 IN RS0 RS0 AE07 IN REQ0 REQA0 LEN0 AE09 IN OUT REQ3 ASZ0 DSZ0 AE11 IN OUT SBSY SBSY AE13 IN OUT LOCK LOCK AE15 N C N C AE17 BPRI BPRI AE19 IN TRST TRST AE21 IN BPM2 BPM2 AE23 IN OUT GND GND AE24 IN PMI PMI AE25 IN GND GND AF01 IN TERM FSBT AF02 IN OUTEN OUTEN AF04 IN Power pod signal GND GND AF05 IN RSP RSP AF06 IN GND GND AF07 IN INIT INIT AF08 IN GND GND AF09 IN REQ1 WSNP D C LEN1 AF10 IN OUT...

Page 63: ...G GND GND AG10 IN N C AG11 GND GND AG12 IN BCLKp CLK AG13 IN GND GND AG14 IN CPUPRES CPUPRES AG15 OUT Power pod signal GND GND AG16 IN N C AG17 GND GND AG18 IN N C AG19 GND GND AG20 IN N C AG21 GND GND AG22 IN IGNNE IGNNE AG23 N C GND GND AG24 IN THRMTRIP THRMTRIP AG25 OUT Thermal trip GND GND AH01 IN TUNER 1 AH03 IN N C AH05 TDO TDO AH07 OUT JTAG TMS TMS AH09 IN JTAG N C AH11 BCLKn BCLKN AH13 IN ...

Page 64: ...cessor 9000 and 9100 Series Datasheet Pinout Specifications A20M A20M AH23 N C FERR FERR AH25 OUT Table 3 2 Pin Signal Information Sorted by Pin Location Sheet 15 of 15 Pin Name System Bus Signal Name Pin Location Input Output Notes ...

Page 65: ... power and I O signals from the voltage regulator to the processor through its substrate Socket Alignment Keyways They define package position in X and Y direction with respect to socket for proper alignment of package pins to socket contact holes Pin Shroud Alignment Keyways They define pin shroud position in X and Y direction with respect to processor Pin 1 Indicators Identifies package orientat...

Page 66: ...um Processor 9000 and 9100 Series Datasheet Mechanical Specifications Figure 4 1 Processor Package 001349 IHS Package C L C L D1 Top View A C2 B2 C1 B1 B A1 Front View A H1 G1 J2 J1 H2 G2 Bottom View A25 AH25 AH1 A1 Side View ...

Page 67: ...Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 67 Mechanical Specifications Table 4 1 Processor Package Dimensions Figure 4 2 Package Height and Pin Dimensions ...

Page 68: ...68 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Mechanical Specifications Table 4 2 Processor Package Mechanical Interface Dimensions ...

Page 69: ...Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet 69 Mechanical Specifications Figure 4 3 Processor Package Mechanical Interface Dimensions ...

Page 70: ...ions Note Keepout zones indicate no components will be on the processor package Note Keepout zones indicate no components will be on the processor package Figure 4 4 Processor Package Top Side Components Height Dimensions Figure 4 5 Processor Package Bottom Side Components Height Dimensions ...

Page 71: ...ocessor to MVR Interface Loads 90 Processor Heatsink IHS Processor Heatsink 90 TZ P z P z A Ty Substrate Socket M other Board Y X Z X Table 4 3 Processor Package Load Limits at Power Tab Sheet 1 of 2 Parameter Description Value1 Comments A Final position of the package at the power tab unloaded with respect to system board 3 8 0 1mm Position of the processor power tab is based on the height of the...

Page 72: ...al Number 2D Matrix Mark Tx Allowable torque at the package power tab in X axis 0 57Nm max T y Allowable torque at the package power tab in y direction 1 24 Nm max Torque on the package edge in Y direction is determined by the load applied in Z and the distance from the edge the package to the socket Torque on the package edge in Y direction is determined by the load applied in Z and the distance ...

Page 73: ...ssor bottom side mark for the product is a laser marking on the pin side of the interposer Figure 4 8 shows the placement of the laser marking on the pin side of interposer The processor bottom side mark provides the following information Product ID S Spec Finish Process Order FPO 2D Matrix Mark Figure 4 7 Processor Top Side Marking on IHS ...

Page 74: ...m Processor 9000 and 9100 Series Datasheet Mechanical Specifications Figure 4 8 Processor Bottom Side Marking Placement on Interposer SCALE 2 Laser Marking 2D Matrix Mark see notes SCALE 2 Laser Marking 2D Matrix Mark see notes ...

Page 75: ...he next state when the cooling solution fails to control the processor temperature as this is affected by many factors such as cooling solution performance degradation and processor workload variations 5 1 1 Thermal Alert THRMALERT is a programmable thermal alert signal which is part of the processor system management feature THRMALERT is asserted when the measured temperature from the processor t...

Page 76: ...power to ensure that there are no false trips The processor will signal a continuable MCA when the power draw exceeds a safe operating level Warning Data will be lost if the MVR overheats and shuts down as a result of an extended over power condition Once power trip is activated the processor can continue operation but may continue to signal continuable MCAs as long as the over power condition exi...

Page 77: ... thermocouple for case temperature measurement Table 5 1 Case Temperature Specification Symbol Parameter Core Frequency Minimum Maximum Unit Notes Tcase Case Temperature 1 6GHz 24MB 5 76 C 1 6GHz 18MB 5 76 C 1 6GHz 9MB 5 76 C 1 42GHz 12MB 5 76 C 1 4GHz 12MB 5 76 C 1 6GHz 6MB 5 74 C Figure 5 2 Itanium Processor Package Thermocouple Location All dimensions are measured in mm Not to scale 001103a The...

Page 78: ...78 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Thermal Specifications ...

Page 79: ...r system thermal monitoring and management The thermal sensing device on the processor provides an accurate means of acquiring an indicator of the junction temperature of the processor core die The thermal sensing device is connected to the anode and cathode of the processor on die thermal diode SMBus implementation on the processor uses the clock and data signals as defined by SMBus specification...

Page 80: ...on may vary 2 For use in general understanding of the architecture 000668b Processor Information ROM A0 A1 A2 SC SD VCC 10K 10K 3 3V Scratch EEPROM A0 A1 A2 SD WP VCC SC 10K 10K 10K Thermal Sensing Device VCC A0 A1 SC SD STBY ALERT SMA0 SMA1 SMA2 3 3V SMSD SMSC THRMALERT Core THERMDA THERMDC Stuffing Options 3 3V System Board 10K SMWP System Board 3 3V 10K Intel Itanium 2 Processor ...

Page 81: ...set the Hi Z state for SMA2 the pin must be left floating The system should drive SMA1 and SMA0 and will be pulled low if not driven by the 10 k pull down resistor on the processor substrate Attempting to drive either of these signals to a Hi Z state would cause ambiguity in the memory device address decode possibly resulting in the devices not responding thus timing out or hanging the SMBus As be...

Page 82: ...1010 0 0 0 X Scratch EEPROM 1 A2h A3h 1010 0 0 1 X Processor Information ROM 1 A4h A5h 1010 0 1 0 X Scratch EEPROM 2 A6h A7h 1010 0 1 1 X Processor Information ROM 2 A8h A9h 1010 1 0 0 X Scratch EEPROM 3 AAh ABh 1010 1 0 1 X Processor Information ROM 3 ACh ADh 1010 1 1 0 X Scratch EEPROM 4 AEh AFh 1010 1 1 1 X Processor Information ROM 4 Table 6 4 Processor Information ROM Format Sheet 1 of 3 Offs...

Page 83: ...served for future use 000000h 1Eh 16 Maximum Core Frequency Four 4 bit hex digits in MHz 1 GHz 1000h 2 20h 12 Maximum System Bus Frequency Three 4 bit hex digits in MHz 200 MHz 200h 1 22h 16 Core Voltage ID Voltage in four 4 bit hex digits in mV 1500 mV 1500h 1 24h 8 Core Voltage Tolerance High Edge finger tolerance in mV two 4 bit hex digits 1 5 22 mV 22h 1 25h 8 Core Voltage Tolerance Low Edge f...

Page 84: ...future use 00h 66h 8 Checksum 1 byte checksum Add up by byte and take 2 s complement Features 67h 32 IA 32 Processor Core Feature Flags From 32 bit CPUID 4387FBFFh 6Bh 64 Reserved Reserved Processor core feature flags implemented in the Itanium processor family 0000 0000 6380 811Bh 73h 32 Processor Feature Flags All others are reserved 9 Demand Based Switching Enabled 8 Core Level Lockstep Enabled...

Page 85: ...ead After the SMBus host controller receives the data word it responds with an acknowledge This will continue until the SMBus host controller responds with a negative acknowledge and a stop Table 6 7 shows the format of the byte write SMBus packet The page write operates the same way as the byte write except that the SMBus host controller does not send a stop after the first data byte and acknowle...

Page 86: ...mal management purposes The temperature data from the thermal sensor can be read out digitally using an SMBus read command see Section 6 6 The thermal sensor detects when SMBus power is applied to the processor and resets itself at power up The thermal sensing device also contains alarm registers to store thermal reference threshold data These values can be individually programmed on the thermal s...

Page 87: ... the five packet types In these tables S represents the SMBus start bit P represents a stop bit Ack represents an acknowledge and represents a negative acknowledge The shaded bits are transmitted by the thermal sensor and the unshaded bits are transmitted by the SMBus host controller Table 6 13 shows the encoding of the command byte Table 6 8 Write Byte SMBus Packet S Address Write Ack Command Ack...

Page 88: ...gister a configuration register a conversion rate register and other reserved registers The following subsections describe the registers in detail 6 7 1 Thermal Reference Registers The processor core and thermal sensing device internal thermal reference registers contain the thermal reference value of the thermal sensing device and the processor core thermal diodes This value ranges from 127 to 12...

Page 89: ...s the operating mode standby vs auto convert of the thermal sensing device Table 6 15 shows the format of the configuration register If the RUN STOP bit is set high then the thermal sensing device immediately stops converting and enters standby mode The thermal sensing device will still perform analog to digital conversions in standby mode when it receives a one shot command If the RUN STOP bit is...

Page 90: ... between conversion rate register values and the conversion rate As indicated in Table 6 16 the conversion rate register is set to its default state of 02h 0 25 Hz nominally when the thermal sensing device is powered up There is a 25 error tolerance between the conversion rate indicated in the conversion rate register and the actual conversion rate Table 6 16 Thermal Sensing Device Conversion Rate...

Page 91: ...al On the active to inactive transition of RESET the processors sample the A 49 3 pins to determine their power on configuration A 1 2 A20M I A20M is no connect and is ignored in the processor system environment A 1 3 ADS I O The Address Strobe ADS signal is asserted to indicate the validity of the transaction address on the A 49 3 REQ 5 0 AP 1 0 and RP pins All bus agents observe the ADS activati...

Page 92: ...ed The ATTR 2 0 are driven based on the memory type Please refer to Table A 2 A 1 7 BCLKp BCLKn I The BCLKp and BCLKn differential clock signals determine the bus frequency All agents drive their outputs and latch their inputs on the differential crossing of BCLKp and BCLKn on the signals that are using the common clock latched protocol BCLKp and BCLKn indirectly determine the internal clock frequ...

Page 93: ...t specified in the Request Phase except the Bus Invalidate Line BIL transaction A BIL transaction may return one cache line 128 bytes A 1 9 BERR I O The Bus Error BERR signal can be asserted to indicate a recoverable error with global MCA BERR assertion conditions are configurable at the system level Configuration options enable BERR to be driven as follows Asserted by the requesting agent of a bu...

Page 94: ...nts might need to request a bus stall at the same time BNR is a wired OR signal In order to avoid wired OR glitches associated with simultaneous edge transitions driven by multiple drivers BNR is asserted and sampled on specific clock edges A 1 12 BPM 5 0 I O The BPM 5 0 signals are system support signals used for inserting breakpoints and for performance monitoring They can be configured as outpu...

Page 95: ...c owner lowest priority in the next arbitration event A new arbitration event occurs either when a symmetric agent asserts its BREQn on an Idle bus all BREQ 3 0 previously deasserted or the current symmetric owner deasserts BREQn to release the bus ownership to a new bus owner n On a new arbitration event all symmetric agents simultaneously determine the new symmetric owner using BREQ 3 0 and the ...

Page 96: ... 3 Data signals that are not valid for a particular transfer must still have correct ECC if data bus error checking is enabled The data driver asserts DRDY to indicate a valid data transfer A 1 19 D C I O The Data Code D C signal is used to indicate data 1 or code 0 on REQa 1 only during Memory Read transactions A 1 20 DBSY I O The Data Bus Busy DBSY signal is asserted by the agent that is respons...

Page 97: ...s but Ab 20 16 is only defined for deferrable transactions DEN asserted DID 9 0 is also transferred on Aa 25 16 during the first clock of the Request Phase for Deferred Reply transactions The Deferred Identifier defines the token supplied by the requesting agent DID 9 and DID 8 5 carry the agent identifiers of the requesting agents always valid and DID 4 0 carry a transaction identifier associated...

Page 98: ... the Data Ready signal This copy of the Data Phase data ready signal DRDY_C1 is an output only A 1 30 DRDY_C2 O DRDY is a copy of the Data Ready signal This copy of the Data Phase data ready signal DRDY_C2 is an output only A 1 31 DSZ 1 0 I O The Data Size DSZ 1 0 signals are transferred on REQb 4 3 signals in the second clock of the Request Phase by the requesting agent The DSZ 1 0 signals define...

Page 99: ...us agent can assert both HIT and HITM together to indicate that it requires a snoop stall The stall can be continued by reasserting HIT and HITM together A 1 37 ID 9 0 I The Transaction ID ID 9 0 signals are driven by the deferring agent The signals in the two clocks are referenced IDa 9 0 and IDb 9 0 During both clocks ID 9 0 signals are protected by the IP0 parity signal for the first clock and ...

Page 100: ...ock and IP 1 protects the IDb 9 2 0 and IDS signals on the second clock A 1 43 LEN 2 0 I O The Data Length LEN 2 0 signals are transmitted using REQb 2 0 signals by the requesting agent in the second clock of Request Phase LEN 2 0 defines the length of the data transfer requested by the requesting agent as shown in Table A 9 The LEN 2 0 HITM and RS 2 0 signals together define the length of the act...

Page 101: ...his allows a memory controller to ignore memory updates due to implicit writebacks A 1 48 PMI I The Platform Management Interrupt PMI signal triggers the highest priority interrupt to the processor PMI is usually used by the system to trigger system events that will be handled by platform specific firmware A 1 49 PWRGOOD I The Power Good PWRGOOD signal must be deasserted L during power on and must...

Page 102: ... REQ 5 0 A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low This definition allows parity to be high when all covered signals are high Table A 10 Transaction Types Defined by REQa REQb Signals Transaction REQa 5 0 REQb 5 0 5 4 3 2 1 0 5 4 3 2 1 0 Deferred Reply 0 0 0 0 0 0 0 x x x x x Reserved 0 0 0 0 0 1 0 x x x x x Int...

Page 103: ...sed SBSY is replicated three times to enable partitioning of data paths in the system agents This copy of the Strobe Bus Busy signal SBSY is an input as well as an output A 1 56 SBSY_C1 O SBSY is a copy of the Strobe Bus Busy signal This copy of the Strobe Bus Busy signal SBSY_C1 is an output only A 1 57 SBSY_C2 O SBSY is a copy of the Strobe Bus Busy signal This copy of the Strobe Bus Busy signal...

Page 104: ...MTRIP signal Once THRMTRIP is asserted the platform must assert RESET to protect the physical integrity of the processor A 1 64 THRMALERT O THRMALERT is asserted when the measured temperature from the processor thermal diode equals or exceeds the temperature threshold data programmed in the high temp THIGH or low temp TLOW registers on the sensor This signal can be used by the platform to implemen...

Page 105: ...nals Table A 12 Output Signals Name Active Level Clock Signal Group CPUPRES Low Platform DBSY_C1 Low BCLKp Data DBSY_C2 Low BCLKp Data DRDY_C1 Low BCLKp Data DRDY_C2 Low BCLKp Data FERR Low Asynchronous PC Compatibility IERR Mode SBSY_C1 Low BCLKp Data SBSY_C2 Low BCLKp Data TDO High TCK TAP THRMTRIP Low Asynchronous Error THRMALERT Low Asynchronous Error Table A 13 Input Signals Sheet 1 of 2 Name...

Page 106: ...Input Output Signals Single Driver Sheet 1 of 2 Name Active Level Clock Signal Group Qualified A 49 3 Low BCLKp Request ADS ADS 1 ADS Low BCLKp Request Always AP 1 0 Low BCLKp Request ADS ADS 1 ASZ 1 0 Low BCLKp System Bus ADS ATTR 3 0 Low BCLKp System Bus ADS 1 BE 7 0 Low BCLKp System Bus ADS 1 BR0 Low BCLKp System Bus Always BPM 5 0 Low BCLKp Diagnostic Always CCL Low BCLKp System Bus ADS 1 D 12...

Page 107: ...s STBp 7 0 Low Data Always WSNP Low BCLKp System Bus ADS Table A 15 Input Output Signals Multiple Driver Name Active Level Clock Signal Group Qualified BNR Low BCLKp System Bus Always BERR Low BCLKp Error Always BINIT Low BCLKp Error Always HIT Low BCLKp Snoop Snoop Phase HITM Low BCLKp Snoop Snoop Phase TND Low BCLKp Snoop Always Table A 14 Input Output Signals Single Driver Sheet 2 of 2 Name Act...

Page 108: ...108 Dual Core Intel Itanium Processor 9000 and 9100 Series Datasheet Signals Reference ...

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