Stanford Research Systems SR785, Руководство по эксплуатации и программированию

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Status Word Definitions 5-125
SR785 Dynamic Signal Analyzer
following a service request. The serial poll automatically clears the service
request. Subsequent serial polls will return SRQ cleared (0) until another service
request occurs. Polling the status word and reading it with *STB? can return
different values for SRQ. When serial polled, SRQ indicates a service request
has occurred. When read with *STB?, SRQ indicates that an enabled status bit is
set.
Service Requests (SRQ)
A GPIB service request (SRQ) will be generated whenever a bit in both the
Serial Poll status word AND Serial Poll enable register is set. Use *SRE to set
bits in the Serial Poll enable register. A service request is only generated when
an enabled Serial Poll status bit becomes set (changes from 0 to 1). An enabled
status bit which becomes set and remains set will generate a single SRQ. If
another service request from the same status bit is desired, the requesting status
bit must first be cleared. In the case of the INST, DISP, INPT, IERR and ESB
bits, this means clearing the enabled bits in the Instrument, Display, Input, Error
or Standard Event status words (by reading them) or clearing the appropriate bits
in the corresponding enable registers. Multiple enabled bits in these status words
will generate a single SRQ. Another SRQ (from INST, DISP, INPT, IERR or
ESB) can only be generated after clearing the INST, DISP, INPT, IERR or ESB
bits in the Serial Poll status word.
The controller should respond to the SRQ by performing a serial poll to read the
Serial Poll status word to determine the requesting status bit. Bit 6 (SRQ) will be
reset by the serial poll.
For example, to generate a service request when a TRIGGER occurs, bit 0 in the
Instrument Status enable register needs to be set (INSE 1 command) and bit 0 in
the Serial Poll enable register must be set (*SRE 1 command). When a trigger
occurs, bit 0 in the Instrument status word is set. Since bit 0 in the Instrument
status word AND enable register are set, this ALSO sets bit 0 (INST) in the
Serial Poll status word. Since bit 0 in the Serial Poll status word AND enable
register are set, an SRQ is generated. Bit 6 (SRQ) in the Serial Poll status word
is set. Further triggering will not generate another SRQ until the TRIGGER
status bit is cleared. The TRIGGER status bit is cleared by reading the
Instrument status word (with INST?) or clearing bit 0 in the Instrument status
enable register (with INSE). Presumably, the controller is alerted to the trigger
via the SRQ, performs a serial poll to clear the SRQ, does something in response
to the trigger (read data for example) and then clears the TRIGGER status bit by
reading the Instrument status register. A subsequent trigger will then generate
another SRQ.