Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 281
−
Negative counter is reloaded with the value set in the reload register ADC12Bn_PCCTRL0 to
63.PCTNRL when:
−
Any positive event occurs
−
"1" is written to dedicated ADC12Bn_PCIRQC0 to 1.PCIRQC63 to 0 bit
−
The positive counter reaches zero and PCIRQ flag is set. The negative counter will hold the
reload value as long as PCIRQ flag is not cleared.
The Figure 3-15 shows the operation of the pulse detection function for channel 0 with
ADC12Bn_CHCTRL0.RCINVSEL = "0" configured for outside range, reload register
ADC12Bn_PCCTRL0.PCTPRL = "101" and reload register ADC12Bn_PCCTRL0.PCTNRL = "011".
Figure 3-15 Example of Pulse Detection Operation
a) Reload counters with appropriate reload value by writing "1" to ADC12Bn_PCIRQC0.PCIRQC0.
b) Positive counter decrements with positive events.
c) Positive counter expires (becomes equal to "0"), the pulse counter interrupt flag PCIRQ is set.
d) A series of negative events does not decrement the negative counter as the PCIRQ flag is set.
e) The pulse counter interrupt flag PCIRQ is cleared and the positive as well as the negative counter are
reloaded.
f) Positive counter expires and PCIRQ flag is to "1".
g) Software clears PCIRQ flag and reloads positive and negative counter.
h) Negative event decrements negative counter.
i) Negative counter expires and reloads positive counter.
j) Positive counter decrements and negative counter reloads with positive event.
5
3
0
1
Upper
Threshold
Lower
Threshold
Pos : counter
Neg : counter
PCIRQ
PCIRQC
4
3
0
0
3
3
0
0
2
3
0
0
1
3
0
0
a b
0
3
1
0
0
3
1
0
0
3
1
0
c d e
5
3
0
1
4
3
0
0
3
3
0
0
2
3
0
0
1
3
0
0
0
3
1
0
0
3
1
0
f
0
3
1
0
g
5
3
0
1
4
3
0
0
3
3
0
0
2
3
0
0
2
2
0
0
h
2
1
0
0
5
0
0
0
4
3
0
0
i j
Time
Range comparator threshold / Conversion result