Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 33:Graphics Subsystem
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1193
3.
Operation of the Graphics Subsystem
This section describes the operation of the Graphics Subsystem.
3.1.
Common Setup
3.1.1.
Configuration Register Clock Setup
The clock frequency for the configuration registers in the graphics subsystem can be setup using register
field ConfigClockSelect in the SubsysCtrl. It specifies the divider used to generate the configuration
clock from the High Performance Bus Matrix clock. The minimum allowed divider setting is 2 (maximum
allowed configuration clock frequency is half the High Performance Bus Matrix clock frequency).
The configuration clock can be changed at any time (e.g. also when transfers are in progress), but note
that configuration access bandwidth and latency are greatly influenced by this setting.
3.1.2.
Display Clock Setup
There are two display clock management units available in the Subsystem Control module of the graphics
subsystem. They are both identical. They contain clock measurement utility to determine the best
possible clock divider for direct capture to display use cases to match the generated display clock as
close as possible to the input capture clock. They also contain clock generation utility to generate the
display clock from the input
reference clock by using a fixed point divider. In addition the generated display clock can be shifted
against the output display data to allow creation of sufficient margin for setup and hold times at the
connected external device.