Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 26:PCMPWM
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 981
Single or Double Output Mode
The PCMPWM module supports two ways of processing the PCM data samples. In single output mode
each PCM data sample is read from the FIFO buffer and then processed by the conversion unit. In double
output mode each PCM data sample is processed twice. I.e. the same PCM data sample is used for two
PWM cycles. The double output mode enables doubling of the PWM output frequency at the same PCM
sample data rate.
The single/double output mode is independent of the mono/stereo mode setting.
Behavior in Debug Mode
The PCMPWM module supports debug mode. If enabled, the module stops converting PCM data
samples after the one in progress and instead simply outputs a silent signal on both channels. The silent
signal corresponds to a continuous stream of PCM data samples with the value of zero. In this mode no
PCM samples are read from the FIFO buffer. However, new sample data may still be written to the FIFO
buffer.
If the module's support for debug mode is not enabled, the PCMPWM module continues with regular
PCM data sample conversion and PWM signal output.
DMA Mode
The PCM data samples may be transferred to the PCMPWM module via DMA. For this the DMA mode
must be enabled by setting the PCMPWMi_CONTROL:DMAEN bit. The transfer works fully
autonomously without any CPU intervention. The transfer takes place in chunks. The respective
maximum number of 32-bit words per transfer is defined by PCMPWMi_CONTROL:FEST + 1. If the
number of free entries in the FIFO buffer exceeds the number specified in PCMPWMi_CONTROL:FEST,
a DMA transfer is requested by the PCMPWM module. The DMA then may fill up the full number of
entries given by PCMPWMi_CONTROL:FEST + 1.
To set up the PCMPWM module for a DMA data transfer, the DMA unit must be configured for block
transfer mode. The block size configured in the DMA must match PCMPWMi_CONTROL:FEST + 1. The
PCMPWM module will then assert the PCMPWM_i_DMA_REQ output when the number of free entries in
the FIFO buffer exceeds the value given by FEST. PCMPWM_i_DMA_REQ stays active until the DMA
acknowledges the request by asserting PCMPWM_i_DMA_REQ_ACK. After the DMA has transferred
FEST + 1 PCM data samples to the FIFO buffer, the PCMPWM will again assert the
PCMPWM_i_DMA_REQ line again when the required number of free FIFO buffer entries is available.
The PCMPWM module keeps track of the number of transferred data words by itself. There is an internal
down counter for this purpose which is reloaded with the value of FEST + 1 when
PCMPWM_i_DMA_REQ is asserted. It is decremented with each word written to the FIFO buffer. When
the counter reaches zero the transfer is complete and another DMA transfer may be requested. It is an
error if the DMA writes data to the FIFO while the down counter is zero. This is condition is flagged as a
DMA block error in the interrupt status register.
Silence Mode
By setting the PCMPWMi_CONTROL:SILENCE trigger, the module is set to silence mode. When this
mode is triggered, the register holding the PCM sample to be converted is cleared to 0 and the reading
from the FIFO is stopped. Also the FIFO is flushed. The FIFO can then be filled again via DMA or the CPU.
As soon as the number of empty entries in the FIFO is equal or less than PCMPWMi_CONTROL:FEST,
reading from the FIFO is resumed.