Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 24:Inter-IC Sound (I2S)
926 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.1.
Reception FIFO Data Register (I2Sn_RXFDAT0 to 15)
These registers are reception FIFO registers that can maintain up to 66 words (simultaneous transfer
mode) or 132 words (reception only mode). There are 16 such registers, all consecutively placed in the
register map. This is to support AHB burst transfers. Read access to any of the I2Sn_RXFDAT0 to 15
registers returns the word from reception FIFO. Each of these 16 registers are identical in function. Only
one register (i.e. I2Sn_RXFDAT0) is explained here.
Reception FIFO Data Register 0 (I2Sn_RXFDAT0)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME RXDATA[31] RXDATA[30] RXDATA[29] RXDATA[28] RXDATA[27] RXDATA[26] RXDATA[25] RXDATA[24]
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME RXDATA[23] RXDATA[22] RXDATA[21] RXDATA[20] RXDATA[19] RXDATA[18] RXDATA[17] RXDATA[16]
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME RXDATA[15] RXDATA[14] RXDATA[13] RXDATA[12] RXDATA[11] RXDATA[10] RXDATA[9] RXDATA[8]
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME RXDATA[7] RXDATA[6] RXDATA[5] RXDATA[4] RXDATA[3] RXDATA[2] RXDATA[1] RXDATA[0]
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] RXDATA : Receive Data
The word received from serial bus is written to reception FIFO.
When frame is 1 sub frame construction and word length set to I2Sn_MCR0REG:S0WDL is 32 bits or
less (16 bits when I2Sn_CNTREG:RHLL register is "1"), it is written to reception FIFO after higher order
bit is extended.
When frame is 2 sub frame construction and word length set to I2Sn_MCR0REG:S0WDL is 32 bits or
less (16 bits when I2Sn_CNTREG:RHLL register is "1"), reception data of sub frame "0" is written to
reception FIFO after higher order bit is extended.
For the case that word length set to I2Sn_MCR0REG:S1WDL is 32 bits or less, reception data of sub
frame 1 is written to reception FIFO after higher order bit is extended.