Cypress S6J3200 Series, Руководство пользователя

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CHAPTER 24:Inter-IC Sound (I2S)
946 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Bit Description
0 Interrupt to CPU by I2Sn_STATUS:RXFI is not masked
1 Interrupt to CPU by I2Sn_STATUS:RXFI is masked
[bit15:12] read0 : -
[bit11:8] TFTH : Tx FIFO Threshold
Threshold value of transmission FIFO is set.
Empty space of transmission FIFO is more than threshold value and I2Sn_INTCNT: Interrupt to CPU
occurs.
Empty space of transmission FIFO is more than threshold value, previous Tx DMA block transfer has
completed, there is no Tx block size error I2Sn_INTCNT:TXFDM is "0": DMA is requested to DMAC.
Note:
−
These bits must not be changed during DMA transfers
[bit7:6] read0 : -
[bit5:4] RPTMR : Rx Completion Timer
This is packet reception completion timer setting bit which sets time-out value of the internal reception
completion timer.
Reception FIFO is not empty and number of its data is smaller than or equal to threshold value: the
timer always counts up.
Reception FIFO is empty or the data value is more than threshold value: the timer is cleared.
When the timer times out, I2Sn_STATUS:EOPI bit is set to "1".
The timer becomes "00" by software reset.
Bit Description
00 0 (the timer is not in operation)
01 54000 internal clock cycles
10 108000 internal clock cycles
11 216000 internal clock cycles
[bit3:0] RFTH : Rx FIFO Threshold
Threshold value of reception FIFO is set.
Number of receive words in reception FIFO is more than threshold value and I2Sn_INTCNT: Interrupt
to CPU occurs.
Number of receive words in reception FIFO is more than threshold value, previous Rx DMA block
transfer has completed, there is no Rx block size error and I2Sn_INTCNT:RXFDM is "0": DMA is
requested to DMAC.
Note:
−
These bits must not be changed during DMA transfers